Patents by Inventor John C. Estes
John C. Estes has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8159314Abstract: An actively tuned filter providing a constant bandwidth at a plurality of frequencies. The filter includes first and second electromagnetically coupled coiled resonators, each resonator having an open end configured to receive an input and a shorted end configured to connect the resonator to a ground. The filter further includes a variable capacitance allowing selection of a capacitance to be applied to the first and second resonators, each variable capacitance being connected to the shorted end of the first and second resonators between the resonator and the ground where the axes of the coils of the first and second resonators are aligned along a single axis.Type: GrantFiled: August 4, 2008Date of Patent: April 17, 2012Assignee: Rockwell Collins, Inc.Inventor: John C. Estes
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Patent number: 7528686Abstract: A tunable filter includes a first resonator; a second resonator; and, a conductive grid assembly electrically coupled to the first and second resonators and coupled to ground. The conductive grid assembly alters the coupling between the first and second resonators. The conductive grid assembly preferably includes a conductive grid element electrically coupled to the first and second resonators; and, a ground coupling element connected between the conductive grid element and ground for altering the coupling between the conductive grid element and ground.Type: GrantFiled: November 21, 2007Date of Patent: May 5, 2009Assignee: Rockwell Collins, Inc.Inventor: John C. Estes
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Patent number: 7221244Abstract: An exemplary system and method for providing differential adjustment of the height of a multilayer substrate in localized areas for improved Q-factor performance of RF devices is disclosed as comprising inter alia: a multilayer substrate (200); an RF component (210) embedded in the substrate (200); a surface mounted component (220); and an RF shield (260) disposed next to the surface mounted component (220), wherein the height of the shield (260) does not extend substantially beyond the height of the surface mounted component (220). Disclosed features and specifications may be variously controlled, configured, adapted or otherwise optionally modified to further improve or otherwise optimize Q, RF performance and/or material characteristics.Type: GrantFiled: September 28, 2005Date of Patent: May 22, 2007Assignee: Motorola, Inc.Inventors: John C. Estes, Rodolfo Lucero, Anthony M. Pavio
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Patent number: 6971162Abstract: An exemplary system and method for providing differential adjustment of the height of a multilayer substrate in localized areas for improved Q-factor performance of RF devices is disclosed as comprising inter alia: a multilayer substrate (200); an RF component (210) embedded in the substrate (200); a surface mounted component (220); and an RF shield (260) disposed next to the surface mounted component (220), wherein the height of the shield (260) does not extend substantially beyond the height of the surface mounted component (220). Disclosed features and specifications may be variously controlled, configured, adapted or otherwise optionally modified to further improve or otherwise optimize Q, RF performance and/or material characteristics.Type: GrantFiled: May 13, 2003Date of Patent: December 6, 2005Assignee: Motorola, Inc.Inventors: John C. Estes, Rodolfo Lucero, Anthony M. Pavio
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Publication number: 20040228099Abstract: An exemplary system and method for providing differential adjustment of the height of a multilayer substrate in localized areas for improved Q-factor performance of RF devices is disclosed as comprising inter alia: a multilayer substrate (200); an RF component (210) embedded in the substrate (200); a surface mounted component (220); and an RF shield (260) disposed next to the surface mounted component (220), wherein the height of the shield (260) does not extend substantially beyond the height of the surface mounted component (220). Disclosed features and specifications may be variously controlled, configured, adapted or otherwise optionally modified to further improve or otherwise optimize Q, RF performance and/or material characteristics.Type: ApplicationFiled: May 13, 2003Publication date: November 18, 2004Inventors: John C. Estes, Rodolfo Lucero, Anthony M. Pavio
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Patent number: 6803836Abstract: A multilayer ceramic structure (30) includes a first ceramic layer (32), a second ceramic layer (34) adjacent to the first ceramic layer, and a transmission line (38) formed between the first and second ceramic layers. The transmission line includes first and second portions (44, 46) having a first width, third and fourth portions (47, 48) formed between the first and second portions and having a second width that is narrower than the first width, and a fifth portion (49) formed between the third and fourth portions. A probe (40), comprising a conductively filled via, is attached at one end to the fifth portion, the probe passing through the second ceramic layer for providing a test point (42). The structure compensates for return loss induced by the probe.Type: GrantFiled: September 27, 2002Date of Patent: October 12, 2004Assignee: Freescale Semiconductor, Inc.Inventors: John C. Estes, Rudolfo Lucero, Anthony M. Pavio
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Publication number: 20040061576Abstract: A multilayer ceramic structure (30) includes a first ceramic layer (32), a second ceramic layer (34) adjacent to the first ceramic layer, and a transmission line (38) formed between the first and second ceramic layers. The transmission line includes first and second portions (44, 46) having a first width, third and fourth portions (47, 48) formed between the first and second portions and having a second width that is narrower than the first width, and a fifth portion (49) formed between the third and fourth portions. A probe (40), comprising a conductively filled via, is attached at one end to the fifth portion, the probe passing through the second ceramic layer for providing a test point (42). The structure compensates for return loss induced by the probe.Type: ApplicationFiled: September 27, 2002Publication date: April 1, 2004Inventors: John C. Estes, Rudolfo Lucero, Anthony M. Pavio
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Patent number: 6664606Abstract: A method of utilizing passive circuit components in an integrated circuit comprising the steps of providing a plurality of integrated capacitive elements and a plurality of integrated inductive elements interconnected to form an electrical circuit wherein each inductive element has a width and creates a circumferential magnetic field. Each integrated inductive element is oriented such that the circumferential magnetic field is parallel to the plane of each adjacent integrated capacitive element and parallel to the width of the integrated inductive element so that the resistance of the electrical circuit is decreased and the quality factor is increased.Type: GrantFiled: April 23, 2002Date of Patent: December 16, 2003Assignee: Motorola, Inc.Inventor: John C. Estes
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Patent number: 6664935Abstract: A broadband impedance matching integrated circuit apparatus comprising an alternating current ground plane, a direct current ground plane positioned proximate to the alternating current ground plane, a first conductive transmission line positioned a distance from the alternating current and direct current ground planes, a dielectric material layer with a thickness positioned on the first conductive transmission line, a second conductive transmission line positioned on the dielectric material layer wherein the first and second conductive transmission lines are electrically interconnected to behave as an electromagnetically coupled tapped autotransformer.Type: GrantFiled: July 31, 2002Date of Patent: December 16, 2003Assignee: Motorola, Inc.Inventors: William John Thompson, Anthony M. Pavio, Lei Zhao, John C. Estes
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Patent number: 6653911Abstract: A stripline integrated circuit apparatus comprising a first ground plane, a stripline section positioned on the first ground plane, the stripline section including N stripline regions where N is a whole number greater than or equal to one, wherein each stripline region includes a stripline sandwiched therebetween a first dielectric layer with a thickness and a second dielectric layer with a thickness where each adjacent stripline is connected in parallel, wherein each adjacent stripline region is separated by a ground plane, a second ground plane positioned on the stripline region, and wherein the plurality of stripline sections are formed and electrically connected in series. The distances between the striplines and the ground planes are adjusted to vary the input and output impedance.Type: GrantFiled: April 10, 2002Date of Patent: November 25, 2003Assignee: Motorola, Inc.Inventors: John C. Estes, Lei Zhao, Anthony M. Pavio, William J. Thompson
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Publication number: 20030197244Abstract: A method of utilizing passive circuit components in an integrated circuit comprising the steps of providing a plurality of integrated capacitive elements and a plurality of integrated inductive elements interconnected to form an electrical circuit wherein each inductive element has a width and creates a circumferential magnetic field. Each integrated inductive element is oriented such that the circumferential magnetic field is parallel to the plane of each adjacent integrated capacitive element and parallel to the width of the integrated inductive element so that the resistance of the electrical circuit is decreased and the quality factor is increased.Type: ApplicationFiled: April 23, 2002Publication date: October 23, 2003Inventor: John C. Estes
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Publication number: 20030193376Abstract: A stripline integrated circuit apparatus comprising a first ground plane, a stripline section positioned on the first ground plane, the stripline section including N stripline regions where N is a whole number greater than or equal to one, wherein each stripline region includes a stripline sandwiched therebetween a first dielectric layer with a thickness and a second dielectric layer with a thickness where each adjacent stripline is connected in parallel, wherein each adjacent stripline region is separated by a ground plane, a second ground plane positioned on the stripline region, and wherein the plurality of stripline sections are formed and electrically connected in series. The distances between the striplines and the ground planes are adjusted to vary the input and output impedance.Type: ApplicationFiled: April 10, 2002Publication date: October 16, 2003Inventors: John C. Estes, Lei Zhao, Anthony M. Pavio, William J. Thompson
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Patent number: 5818313Abstract: A laminated lowpass filter (100) is disclosed. The filter (100) has: a stack of dielectric substrates (301-312) having a ground via (118); a pi network coupled between an input (202) and an output (202'); a first leg comprising a first transmission line (608) and a first capacitance (C1) connected to a top ground plane (GP1); a second leg comprising a second transmission line (608') and a second capacitance (C2) connected to a bottom ground plane (GP2); a middle leg including a transmission line (606) is between the first and second leg; the single point ground plane configuration prevents ground loops and minimizes the passage of stray signals through the laminated lowpass filter (100).Type: GrantFiled: January 31, 1997Date of Patent: October 6, 1998Assignee: Motorola Inc.Inventors: John C. Estes, Richard Kommrusch, Rong Fong Huang
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Patent number: 5584053Abstract: What is described is a commonly coupled high frequency transmitting/receiving switching module (100). The switching module (100), has a transmitting circuit (102), a receiving circuit (104), an antenna circuit (106), an external circuit (108), a coupling circuit (110) and control circuits (124, 126). The switching module may be switched between one of four circuit paths (202, 204, 206, 208) each path incorporating an integral harmonic filter (210, 212). This structure is adapted for use in a multi-layer ceramic integrated circuit, and provides the advantage of minimizing current consumption with a minimal number of components.Type: GrantFiled: August 4, 1995Date of Patent: December 10, 1996Assignee: Motorola, Inc.Inventors: Richard S. Kommrusch, Rong-Fong Huang, John C. Estes