Patents by Inventor John C. Manton
John C. Manton has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 5999437Abstract: A processor-inclusive memory module (PIMM) is disclosed. In one embodiment of the present invention, the PIMM includes a printed circuit board having first and second opposing surfaces. The printed circuit board also has an address line formed therein. A first SRAM is mounted on the first surface of the printed circuit board. The present PIMM is further comprised of a second SRAM mounted on the second surface of the printed circuit board. The second SRAM is mounted on the second surface of the printed circuit board directly opposite the first SRAM mounted on the first surface of the printed circuit board. The first and second SRAMs are coupled to the address line by respective cache buses. A processor is also mounted on the first surface of the printed circuit board, and is coupled to the address line. In one embodiment of the invention, a heat sink is thermally coupled to the processor. The processor has a plurality of contact pads disposed thereon.Type: GrantFiled: January 27, 1997Date of Patent: December 7, 1999Assignee: Silicon Graphics, Inc.Inventors: David P. Chengson, William L. Schmidt, Unmesh Agarwala, Alan D. Foster, Edward C. Priest, John C. Manton, Ali Mira
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Patent number: 5867419Abstract: A processor-inclusive memory module (PIMM) is disclosed. In one embodiment of the present invention, the PIMM includes a printed circuit board having first and second opposing surfaces. The printed circuit board also has an address line formed therein. A first SRAM is mounted on the first surface of the printed circuit board. The present PIMM is further comprised of a second SRAM mounted on the second surface of the printed circuit board. The second SRAM is mounted on the second surface of the printed circuit board directly opposite the first SRAM mounted on the first surface of the printed circuit board. The first and second SRAMs are coupled to the address line by respective cache buses. A processor is also mounted on the first surface of the printed circuit board, and is coupled to the address line. In one embodiment of the invention, a heat sink is thermally coupled to the processor. The processor has a plurality of contact pads disposed thereon.Type: GrantFiled: July 29, 1997Date of Patent: February 2, 1999Assignee: Silicon Graphics, Inc.Inventors: David P. Chengson, William L. Schmidt, Unmesh Agarwala, Alan D. Foster, Edward C. Priest, John C. Manton, Ali Mira
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Patent number: 5710733Abstract: A processor-inclusive memory module (PIMM) is disclosed. In one embodiment of the present invention, the PIMM includes a printed circuit board having first and second opposing surfaces. The printed circuit board also has an address line formed therein. A first SRAM is mounted on the first surface of the printed circuit board. The present PIMM is further comprised of a second SRAM mounted on the second surface of the printed circuit board. The second SRAM is mounted on the second surface of the printed circuit board directly opposite the first SRAM mounted on the first surface of the printed circuit board. The first and second SRAMs are coupled to the address line by respective cache buses. A processor is also mounted on the first surface of the printed circuit board, and is coupled to the address line. In one embodiment of the invention, a heat sink is thermally coupled to the processor. The processor has a plurality of contact pads disposed thereon.Type: GrantFiled: January 22, 1996Date of Patent: January 20, 1998Assignee: Silicon Graphics, Inc.Inventors: David P. Chengson, William L. Schmidt, Unmesh Agarwala, Alan D. Foster, Edward C. Priest, John C. Manton, Ali Mira
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Patent number: 4742451Abstract: A central processor unit for a digital data processing system that processes prefetched instructions including a conditional branch instruction. The processor includes a fetch unit that has separate portions, one that retrieves operands and the other that retrieves instructions. When the fetch unit fetches a conditional branch instruction, it may continue to prefetch "branch not taken" instructions using the instruction fetch portion. The fetch unit initially uses the operand fetch portion to prefetch "branch taken" instructions. If it is determined that the branch is not taken, the prefetch operation is aborted, otherwise the prefetch operation is allowed to continue to provide the next instruction used by the processor.Type: GrantFiled: May 21, 1984Date of Patent: May 3, 1988Assignee: Digital Equipment CorporationInventors: William F. Bruckert, Tryggve Fossum, John A. DeRosa, Jr., Richard E. Glackemeyer, Allan E. Helenius, John C. Manton
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Patent number: 4604750Abstract: In a data processing system, a memory (32) consists of data words and associated error-correction codes that are independently accessible; it is possible simultaneously to read a data word and write its associated error-correction code. This allows a memory-control circuit (30) immediately to store in the memory (32) a data word sent by a processor (10) while it is concurrently in the process of generating the error-correction code for that data word. The result is that the memory-control circuit (30) can subsequently fetch the newly stored data word before storage of its associated error-correction code is complete. This reduces delays involved in error-correction-code generation. The data word includes not only non-redundant information but also parity bits that both the processor (10) and the memory-control circuit (30) employ to determine whether a data word is correct.Type: GrantFiled: November 7, 1983Date of Patent: August 5, 1986Assignee: Digital Equipment CorporationInventors: John C. Manton, William F. Bruckert, Alfred J. Dellicicchi
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Patent number: 4509115Abstract: A memory unit connected in a data processing system including a central processor unit and an input/output unit. The memory unit is connected to the central processor unit through one port, and to the input/output unit through a second port. When the central processor unit wants to transfer data with the input/output unit, it does so through the memory unit.Type: GrantFiled: April 21, 1982Date of Patent: April 2, 1985Assignee: Digital Equipment CorporationInventors: John C. Manton, Kenneth Okin, Anthony N. Zacconi
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Patent number: 4500958Abstract: A memory unit for connection in a data processing system in which the central processor unit may transfer data to or retrieve data from portions of two storage locations in one transfer. The memory unit has a data rotating and storage network that rotates the data and stores it as necessary for its transfer to or from the addressed storage locations.Type: GrantFiled: April 21, 1982Date of Patent: February 19, 1985Assignee: Digital Equipment CorporationInventors: John C. Manton, Kenneth Okin