Patents by Inventor John C. O'Brien

John C. O'Brien has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240120415
    Abstract: Technologies for a field effect transistor (FET) with a ferroelectric gate dielectric are disclosed. In an illustrative embodiment, a perovskite stack is grown on a buffer layer as part of manufacturing a transistor. The perovskite stack includes one or more doped semiconductor layers alternating with other lattice-matched layers. Growing the doped semiconductor layers on lattice-matched layers can improve the quality of the doped semiconductor layers. The lattice-matched layers can be etched away, leaving the doped semiconductor layers as fins for a ribbon FET. A ferroelectric layer can be conformally grown on the fins, creating a high-quality ferroelectric layer above and below the fins. A gate can then be grown on the ferroelectric layer.
    Type: Application
    Filed: October 1, 2022
    Publication date: April 11, 2024
    Applicant: Intel Corporation
    Inventors: Scott B. Clendenning, Sudarat Lee, Kevin P. O'Brien, Rachel A. Steinhardt, John J. Plombon, Arnab Sen Gupta, Charles C. Mokhtarzadeh, Gauri Auluck, Tristan A. Tronic, Brandon Holybee, Matthew V. Metz, Dmitri Evgenievich Nikonov, Ian Alexander Young
  • Publication number: 20240113220
    Abstract: Technologies for a transistor with a thin-film ferroelectric gate dielectric are disclosed. In the illustrative embodiment, a transistor has a thin layer of scandium aluminum nitride (ScxAl1-xN) ferroelectric gate dielectric. The channel of the transistor may be, e.g., gallium nitride or molybdenum disulfide. In one embodiment, the ferroelectric polarization changes when voltage is applied and removed from a gate electrode, facilitating switching of the transistor at a lower applied voltage. In another embodiment, the ferroelectric polarization of a gate dielectric of a transistor changes when the voltage is past a positive threshold value or a negative threshold value. Such a transistor can be used as a one-transistor memory cell.
    Type: Application
    Filed: September 30, 2022
    Publication date: April 4, 2024
    Applicant: Intel Corporation
    Inventors: Arnab Sen Gupta, Ian Alexander Young, Dmitri Evgenievich Nikonov, Marko Radosavljevic, Matthew V. Metz, John J. Plombon, Raseong Kim, Uygar E. Avci, Kevin P. O'Brien, Scott B. Clendenning, Jason C. Retasket, Shriram Shivaraman, Dominique A. Adams, Carly Rogan, Punyashloka Debashis, Brandon Holybee, Rachel A. Steinhardt, Sudarat Lee
  • Publication number: 20240067519
    Abstract: Example methods, systems, and apparatus described herein provide a minimally invasive technique of controlling shape and stress in a MEMS device. An example method includes depositing a layer of material continuously across a semiconductor wafer, exposing the layer of material to oxygen plasma to increase a relative amount of oxygen within the layer of material; and etching the layer of material after exposing the layer of material to the oxygen plasma.
    Type: Application
    Filed: June 21, 2023
    Publication date: February 29, 2024
    Inventors: John Wesley Hamlin, Kathleen Rose Ferreira, Sean C. O'Brien, Jose A. Martinez
  • Publication number: 20040193643
    Abstract: One aspect of the invention is a method for generating a report that comprises storing data in a database, where the data includes a plurality of requirements associated with an entity and one or more deliverable items. In the database, at least some of the one or more deliverable items are linked with at least one of the requirements. A report is generated in response to the one or more deliverable items and the at least one of the requirements.
    Type: Application
    Filed: March 27, 2003
    Publication date: September 30, 2004
    Inventors: John C. O'Brien, Kathleen A. Zawacki
  • Patent number: 5449069
    Abstract: A surgical instrument rack is provided for improving the efficiency, quality, and safety of the processing and delivery of ring-handled surgical instruments. The rack includes a base having opposing front and rear panels, each having multiple slots therein for supporting the instruments. Each slot in the front panel corresponds to one of the slots in the rear panel so that the end of each of the surgical instruments having the ring handles can be positioned in the slot in the front panel and the opposite end of the instrument can be positioned in the corresponding slot in the rear panel. The instruments can thus be held in an upstanding, parallel, side-by-side arrangement. The base also includes apertures therein near the front panel for receiving a spindle such that the spindle may be extended through the apertures and the first ring handles of the surgical instruments to couple the instruments with the base.
    Type: Grant
    Filed: January 3, 1994
    Date of Patent: September 12, 1995
    Assignee: Nitro-Wear Technology, Inc.
    Inventors: Martin Pijanowski, John C. O'Brien
  • Patent number: 4091136
    Abstract: A synthetic cork-like material for use as a closure for liquid containers which is composed of a fine celled polyolefin foam containing an ionomer and which may be formed by a foaming process.
    Type: Grant
    Filed: May 17, 1976
    Date of Patent: May 23, 1978
    Assignee: Shaw Plastics Corporation
    Inventors: John C. O'Brien, Herbert A. Ehrenfreund