Patents by Inventor John C. Ruttenberg
John C. Ruttenberg has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8924898Abstract: An automated processor design tool uses a description of customized processor instruction set extensions in a standardized language to develop a configurable definition of a target instruction set, a Hardware Description Language description of circuitry necessary to implement the instruction set, and development tools such as a compiler, assembler, debugger and simulator which can be used to develop applications for the processor and to verify it. Implementation of the processor circuitry can be optimized for various criteria such as area, power consumption, speed and the like. Once a processor configuration is developed, it can be tested and inputs to the system modified to iteratively optimize the processor implementation. By providing a constrained domain of extensions and optimizations, the process can be automated to a high degree, thereby facilitating fast and reliable development.Type: GrantFiled: June 9, 2008Date of Patent: December 30, 2014Assignee: Cadence Design Systems, Inc.Inventors: Earl A. Killian, Ricardo E. Gonzalez, Ashish B. Dixit, Monica Lam, Walter D. Lichtenstein, Christopher Rowen, John C. Ruttenberg, Robert P. Wilson, Albert Ren-Rui Wang, Dror Eliezer Maydan
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Patent number: 8875068Abstract: An automated processor design tool uses a description of customized processor instruction set extensions in a standardized language to develop a configurable definition of a target instruction set, a Hardware Description Language description of circuitry necessary to implement the instruction set, and development tools such as a compiler, assembler, debugger and simulator which can be used to develop applications for the processor and to verify it. Implementation of the processor circuitry can be optimized for various criteria such as area, power consumption, speed and the like. Once a processor configuration is developed, it can be tested and inputs to the system modified to iteratively optimize the processor implementation. By providing a constrained domain of extensions and optimizations, the process can be automated to a high degree, thereby facilitating fast and reliable development.Type: GrantFiled: June 9, 2008Date of Patent: October 28, 2014Assignee: Cadence Design Systems, Inc.Inventors: Earl A. Killian, Ricardo E. Gonzalez, Ashish B. Dixit, Monica Lam, Walter D. Lichtenstein, Christopher Rowen, John C. Ruttenberg, Robert P. Wilson, Albert Ren-Rui Wang, Dror Eliezer Maydan
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Automated processor generation system for designing a configurable processor and method for the same
Patent number: 8006204Abstract: An automated processor design tool uses a description of customized processor instruction set extensions in a standardized language to develop a configurable definition of a target instruction set, a Hardware Description Language description of circuitry necessary to implement the instruction set, and development tools such as a compiler, assembler, debugger and simulator which can be used to develop applications for the processor and to verify it. Implementation of the processor circuitry can be optimized for various criteria such as area, power consumption, speed and the like. Once a processor configuration is developed, it can be tested and inputs to the system modified to iteratively optimize the processor implementation. By providing a constrained domain of extensions and optimizations, the process can be automated to a high degree, thereby facilitating fast and reliable development.Type: GrantFiled: March 27, 2006Date of Patent: August 23, 2011Assignee: Tensilica, Inc.Inventors: Earl A. Killian, Ricardo E. Gonzalez, Ashish B. Dixit, Monica Lam, Walter D. Lichtenstein, Christopher Rowen, John C. Ruttenberg, Robert P. Wilson, Albert Ren-Rui Wang, Dror Eliezer Maydan -
Publication number: 20080244506Abstract: An automated processor design tool uses a description of customized processor instruction set extensions in a standardized language to develop a configurable definition of a target instruction set, a Hardware Description Language description of circuitry necessary to implement the instruction set, and development tools such as a compiler, assembler, debugger and simulator which can be used to develop applications for the processor and to verify it. Implementation of the processor circuitry can be optimized for various criteria such as area, power consumption, speed and the like. Once a processor configuration is developed, it can be tested and inputs to the system modified to iteratively optimize the processor implementation. By providing a constrained domain of extensions and optimizations, the process can be automated to a high degree, thereby facilitating fast and reliable development.Type: ApplicationFiled: June 9, 2008Publication date: October 2, 2008Inventors: Earl A. Killian, Richardo E. Gonzalez, Ashish B. Dixit, Monica Lam, Walter D. Lichtenstein, Christopher Rowen, John C. Ruttenberg, Robert P. Wilson, Albert Ren-Ru Wang, Dror Eliezer Maydan
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Publication number: 20080244471Abstract: An automated processor design tool uses a description of customized processor instruction set extensions in a standardized language to develop a configurable definition of a target instruction set, a Hardware Description Language description of circuitry necessary to implement the instruction set, and development tools such as a compiler, assembler, debugger and simulator which can be used to develop applications for the processor and to verify it. Implementation of the processor circuitry can be optimized for various criteria such as area, power consumption, speed and the like. Once a processor configuration is developed, it can be tested and inputs to the system modified to iteratively optimize the processor implementation. By providing a constrained domain of extensions and optimizations, the process can be automated to a high degree, thereby facilitating fast and reliable development.Type: ApplicationFiled: June 9, 2008Publication date: October 2, 2008Inventors: Earl A. Killian, Ricardo E. Gonzalez, Ashish B. Dixit, Monica Lam, Walter D. Lichtenstein, Christopher Rowen, John C. Ruttenberg, Robert P. Wilson, Albert Ren-Rui Wang, Dror Eliezer Maydan
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Patent number: 7065586Abstract: A system and method for scheduling transfers of data through a network, the system comprising a transfer module at each node in the network, the transfer module being configured to schedule data transfers according to available resources at each node. In one embodiment, the transfer module includes a scheduling module, a routing module, and an execution module. The scheduling module at each node evaluates a single hop request in view of objectives, such as a deadline, and the available resources at that node, for example transmit bandwidth, receive bandwidth, and storage space, all of which may change as a function of time.Type: GrantFiled: August 21, 2001Date of Patent: June 20, 2006Assignee: Radiance Technologies, Inc.Inventors: John C. Ruttenberg, Walter D. Lichtenstein, David Agraz, Fouad A. Tobagi, Ashfaq A. Munshi, David Lemke
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Automated processor generation system for designing a configurable processor and method for the same
Patent number: 7020854Abstract: An automated processor design tool uses a description of customized processor instruction set extensions in a standardized language to develop a configurable definition of a target instruction set, a Hardware Description Language description of circuitry necessary to implement the instruction set, and development tools such as a compiler, assembler, debugger and simulator which can be used to develop applications for the processor and to verify it. Implementation of the processor circuitry can be optimized for various criteria such as area, power consumption, speed and the like. Once a processor configuration is developed, it can be tested and inputs to the system modified to iteratively optimize the processor implementation. By providing a constrained domain of extensions and optimizations, the process can be automated to a high degree, thereby facilitating fast and reliable development.Type: GrantFiled: July 2, 2004Date of Patent: March 28, 2006Assignee: Tensilica, Inc.Inventors: Earl A. Killian, Ricardo E. Gonzalez, Ashish B. Dixit, Monica Lam, Walter D. Lichtenstein, Christopher Rowen, John C. Ruttenberg, Robert P. Wilson, Albert Ren-Rui Wang, Dror Eliezer Maydan -
Automated processor generation system for designing a configurable processor and method for the same
Publication number: 20040250231Abstract: An automated processor design tool uses a description of customized processor instruction set extensions in a standardized language to develop a configurable definition of a target instruction set, a Hardware Description Language description of circuitry necessary to implement the instruction set, and development tools such as a compiler, assembler, debugger and simulator which can be used to develop applications for the processor and to verify it. Implementation of the processor circuitry can be optimized for various criteria such as area, power consumption, speed and the like. Once a processor configuration is developed, it can be tested and inputs to the system modified to iteratively optimize the processor implementation. By providing a constrained domain of extensions and optimizations, the process can be automated to a high degree, thereby facilitating fast and reliable development.Type: ApplicationFiled: July 2, 2004Publication date: December 9, 2004Inventors: Earl A. Killian, Ricardo E. Gonzalez, Ashish B. Dixit, Monica Lam, Walter D. Lichtenstein, Christopher Rowen, John C. Ruttenberg, Robert P. Wilson, Albert Ren-Rui Wang, Droe Eliezer Maydan -
Automated processor generation system for designing a configurable processor and method for the same
Patent number: 6760888Abstract: An automated processor design tool uses a description of customized processor instruction set extensions in a standardized language to develop a configurable definition of a target instruction set, a Hardware Description Language description of circuitry necessary to implement the instruction set, and development tools such as a compiler, assembler, debugger and simulator which can be used to develop applications for the processor and to verify it. Implementation of the processor circuitry can be optimized for various criteria such as area, power consumption, speed and the like. Once a processor configuration is developed, it can be tested and inputs to the system modified to iteratively optimize the processor implementation. By providing a constrained domain of extensions and optimizations, the process can be automated to a high degree, thereby facilitating fast and reliable development.Type: GrantFiled: November 1, 2002Date of Patent: July 6, 2004Assignee: Tensilica, Inc.Inventors: Earl A. Killian, Ricardo E. Gonzalez, Ashish B. Dixit, Monica Lam, Walter D. Lichtenstein, Christopher Rowen, John C. Ruttenberg, Robert P. Wilson, Albert Ren-Rui Wang, D{grave over (r)}or Eliezer Maydan -
Automated processor generation system for designing a configurable processor and method for the same
Publication number: 20030208723Abstract: An automated processor design tool uses a description of customized processor instruction set extensions in a standardized language to develop a configurable definition of a target instruction set, a Hardware Description Language description of circuitry necessary to implement the instruction set, and development tools such as a compiler, assembler, debugger and simulator which can be used to develop applications for the processor and to verify it. Implementation of the processor circuitry can be optimized for various criteria such as area, power consumption, speed and the like. Once a processor configuration is developed, it can be tested and inputs to the system modified to iteratively optimize the processor implementation. By providing a constrained domain of extensions and optimizations, the process can be automated to a high degree, thereby facilitating fast and reliable development.Type: ApplicationFiled: November 1, 2002Publication date: November 6, 2003Applicant: TENSILICA, INC.Inventors: Earl A. Killian, Ricardo E. Gonzalez, Ashish B. Dixit, Monica Lam, Walter D. Lichtenstein, Christopher Rowen, John C. Ruttenberg, Robert P. Wilson, Albert Ren-Rui Wang, Dror Eliezer Maydan -
Automated processor generation system for designing a configurable processor and method for the same
Patent number: 6477683Abstract: An automated processor design tool uses a description of customized processor instruction set extensions in a standardized language to develop a configurable definition of a target instruction set, a Hardware Description Language description of circuitry necessary to implement the instruction set, and development tools such as a compiler, assembler, debugger and simulator which can be used to develop applications for the processor and to verify it. Implementation of the processor circuitry can be optimized for various criteria such as area, power consumption, speed and the like. Once a processor configuration is developed, it can be tested and inputs to the system modified to iteratively optimize the processor implementation. By providing a constrained domain of extensions and optimizations, the process can be automated to a high degree, thereby facilitating fast and reliable development.Type: GrantFiled: February 5, 1999Date of Patent: November 5, 2002Assignee: Tensilica, Inc.Inventors: Earl A. Killian, Ricardo E. Gonzalez, Ashish B. Dixit, Monica Lam, Walter D. Lichtenstein, Christopher Rowen, John C. Ruttenberg, Robert P. Wilson, Albert Ren-Rui Wang, Dror Eliezer Maydan -
Publication number: 20020083185Abstract: A system and method for scheduling transfers of data through a network, the system comprising a transfer module at each node in the network, the transfer module being configured to schedule data transfers according to available resources at each node. In one embodiment, the transfer module includes a scheduling module, a routing module, and an execution module. The scheduling module at each node evaluates a single hop request in view of objectives, such as a deadline, and the available resources at that node, for example transmit bandwidth, receive bandwidth, and storage space, all of which may change as a function of time.Type: ApplicationFiled: August 21, 2001Publication date: June 27, 2002Inventors: John C. Ruttenberg, Walter D. Lichtenstein, David Agraz, Fouad A. Tobagi, Ashfaq A. Munshi, David Lemke
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Patent number: 6282633Abstract: A RISC processor implements an instruction set which, in addition to optimizing a relationship between the number of instructions required for execution of a program, clock period and average number of clocks per instruction, also is designed to optimize the equation S=IS * BI, where S is the size of program instructions in bits, IS is the static number of instructions required to represent the program (not the number required by an execution) and BI is the average number of bits per instruction. Compared to conventional RISC architectures, this processor lowers both BI and IS with minimal increases in clock period and average number of clocks per instruction. The processor provides good code density in a fixed-length high-performance encoding based on RISC principles, including a general register with load/store architecture. Further, the processor implements a simple variable-length encoding that maintains high performance.Type: GrantFiled: November 13, 1998Date of Patent: August 28, 2001Assignee: Tensilica, Inc.Inventors: Earl A. Killian, Ricardo E. Gonzalez, Ashish B. Dixit, Monica Lam, Walter D. Lichtenstein, Christopher Rowen, John C. Ruttenberg, Robert P. Wilson
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Patent number: 5491823Abstract: A loop scheduler in a software compiler system for generating a schedule for executing in a target computer loops of instructions contained in a computer program is described. The loop scheduler operates by searching for an optimal loop schedule for executing a particular instruction loop in the target computer. The loop scheduler then identifies loop overhead instructions and non-loop overhead instructions in the particular instruction loop. A replicated loop schedule is generated by the loop scheduler by replicating the non-loop overhead instructions in the loop schedule by a replication factor such that overlap of each operation instance in the optimal loop schedule with itself is prevented. The loop scheduler inserts the loop overhead instructions into the replicated loop schedule to generate a modified loop schedule, and then allocates registers of the target computer to the modified loop schedule.Type: GrantFiled: January 25, 1994Date of Patent: February 13, 1996Assignee: Silicon Graphics, Inc.Inventor: John C. Ruttenberg