Abstract: Circuits, methods, and apparatus that provide highly integrated digital media processors for digital consumer electronics applications. These digital media processors are capable of performing the parallel processing of multiple format audio, video, and graphics signals. In one embodiment, audio and video signals may be received from a variety of input devices or appliances, such as antennas, VCRs, DVDs, and networked devices such as camcorders and modems, while output audio and video signals may be provided to output devices such as televisions, monitors, and networked devices such as printers and networked video recorders. Another embodiment of the present invention interfaces with a variety of devices such as navigation, entertainment, safety, memory, and networking devices. This embodiment can also be configured for use in a digital TV, set-top box, or home server. In this configuration, video and audio streams may be received from a number of cable, satellite, Internet, and consumer devices.

Abstract: Circuits, methods, and apparatus that provide highly integrated digital media processors for digital consumer electronics applications. These digital media processors are capable of performing the parallel processing of multiple format audio, video, and graphics signals. In one embodiment, audio and video signals may be received from a variety of input devices or appliances, such as antennas, VCRs, DVDs, and networked devices such as camcorders and modems, while output audio and video signals may be provided to output devices such as televisions, monitors, and networked devices such as printers and networked video recorders. Another embodiment of the present invention interfaces with a variety of devices such as navigation, entertainment, safety, memory, and networking devices. This embodiment can also be configured for use in a digital TV, set-top box, or home server. In this configuration, video and audio streams may be received from a number of cable, satellite, Internet, and consumer devices.

Abstract: A memory system 107,300 is provided which includes a memory 107 having a data area for storing data words and a mask area 302 for storing a control mask. Mask generation circuitry 301 is provided for generating such a control mask for storage in the mask area 302 of the memory 107. Mask controlled memory read control circuitry 303 is provided which is operable to selectively retrieve from the mask area 302 bits of the mask stored therein and in response selectively retrieve and output data words stored in the data area of the memory 107.

Abstract: A display interface device 20 is provided which includes inputs for receiving video data words, the video data words including control codes for controlling the output format of a display, and a video clock signal received from an associated video controller. A first-in/first-out memory 30 is also provided with a video data word clocked into memory 30 by the first clock and clocked out of memory 30 by a second clock generated from a clock received from an associated graphics controller.

Abstract: A graphics and video controller 105 is provided which includes a dual aperture interface 206 for receiving words of graphics and video pixel data, each word of such data associated with an address directing that word to be processed as either graphics or video data. Circuitry 200, 201, 202, 207, 208 is provided for writing a word of the pixel data received from the interface 206 to a one of the on- and off-screen memory areas corresponding to the address associated with the received word. Circuitry 201, 202 is provided for selectively retrieving graphics and video data from the on-screen and off-screen memory areas. A first pipeline 205 is provided for processing data received from the on-screen area of frame buffer 107 while a second pipeline 204 is provided for processing data retrieved from the off-screen area of the frame buffer.

Abstract: A display interface device 20 is provided which includes inputs for receiving video data words, the video data words including control codes for controlling the output format of a display, and a video clock signal received from an associated video controller. A first-in/first-out memory 30 is also provided with a video data word clocked into memory 30 by the first clock and clocked out of memory 30 by a second clock generated from a clock received from an associated graphics controller.

Abstract: Methods are provided for transferring a stream of video data from a video data source to a display interface unit 20. A video data word is clocked into a first-in-first-out memory 30 by a first clock and clocked out of memory 30 by a second clock generated from a clock received from an associated graphics controller.

Abstract: Circuitry for altering a received data stream as a function of a received factor, the received factor indicative of an output format of the received data stream. Included within the circuitry is a first circuit operable to selectively expand portions of the received data stream as a function of the received factor. Further included within the circuitry is a second circuit operable to dynamically generate a zoom code associated with a selected portion of the received data stream, the zoom code providing direction to an associated device for completing the generation of the output format.

Abstract: A processing system 100 is provided which includes a memory 107 and memory control circuitry 203. Packing circuitry 215 is operable to receive a stream of video data words in a first YUV format and convert those video data words into a plurality of packed words in a second YUV format. Memory control circuitry 203 is operable to simultaneously store the plurality of packed YUV words in memory 107 in the second format along with a plurality of RGB words.

Abstract: A digital video editor employing a single chip special-purpose digital video processing unit (VPU) having the capability to combine several different digital video input signals into a single digital video output signal is disclosed. The VPU comprises a microprocessor operating under a set of instructions which is operative for receiving, storing and manipulating portions of an incoming digital video signal and a delay circuit, coupled to the microprocessor, for delaying execution of a particular instruction if a particular portion upon which the instruction is to operate has not yet been stored. The VPU processes multiple digitized video signals in real time in a time-sharing fashion because its processing speed is substantially greater than the rate at which it receives video data and processes multiple picture elements of a single digital stream simultaneously. In a preferred environment, The VPU operates in conjunction with an IBM compatible personal computer, an inexpensive general purpose computer.

Abstract: A quantization processor (64) is provided that is operable to provide an error diffusion for adjacent output pixels in an output display space. Three quantization processors (300), (302) and (304) are provided for the three colors of the video RGB format. A full adder (312) is provided for receiving both an error signal and an input pixel value. The composite output is input to an input/output error register 328 that is operable to store bits of the output of the adder, determined to be output bits, and also to store the remainder of the bits that are determined to be error or truncated bits. The error or truncated bits are fed back to the input of the full adder. A rounding decoder (306) is operable to receiving a masking word, such that the outputs from the register (326) are either selected as bits to be truncated, provide an error to be added to the next sequential pixel value, or they are selected as outputs. The register (326) is operable to store the error bits for the next sequential cycle.

Abstract: A pixel processor is disclosed which is comprised of a video window generator (VWG) (10). VWG (10) utilizes a conversion section for receiving an input video signal in a YUV 422 video format and converting it to an RGB video format. The conversion section includes a chroma interpolator 56 for converting the YUV 422 video format to a YUV 444 video format, a color converter (58) for converting the YUV 444 video format to an RGB video format, and then to a gamma coding removal block (60) for removing gamma coding. After conversion, the RGB video format signal is then scaled down by a linear resampler block (62) to average information over a predetermined portion of the input display space for output to a predetermined portion of the output display space. The scaled video output is truncated by a quantization processor (64) and then input to a FIFO (66). A control unit (68) controls the operation of the system.

Abstract: A graphics and video controller 105 is provided which includes a dual aperture interface 206 for receiving words of graphics and video pixel data, each word of such data associated with an address directing that word to be processed as either graphics or video data. Circuitry 200, 201, 202, 207, 208 is provided for writing a word of the pixel data received from the interface 206 to a one of the on- and off-screen memory areas corresponding to the address associated with the received word. Circuitry 201, 202 is provided for selectively retrieving graphics and video data from the on-screen and off-screen memory areas. A first pipeline 205 is provided for processing data received from the on-screen area of frame buffer 107 while a second pipeline 204 is provided for processing data retrieved from the off-screen area of the frame buffer.