Abstract: Embodiments of the present invention provide an integrated circuit (IC) having an integrated DC-DC power converter therein. This IC is operable to support the distribution of combined power and data signals in a network environment such as an Ethernet network according to protocols such as the power over Ethernet (PoE) protocol. The IC includes a DC-DC power converter, a power feed circuit, and a network physical layer (PHY) module, wherein the PHY module may contain fine line structures susceptible to damage when exposed to excessive voltages. To prevent or reduce the likelihood of damage to the PHY module from voltages supplied to the DC-DC power converter, a common substrate ground is shared between the IC components.

Abstract: Embodiments of the present invention provide a network device operable to receive a network signal that may include both power and data from a coupled network. This network device includes a network connector and an integrated circuit. The network connector physically couples the network device to the network. An optional protection circuit may provide surge protection or incoming network signals received by the network device through the network connector. An optional switching/rectifying circuit sees the output of the protection circuit and is operable to rectify a power signal when contained within the network signal. The integrated circuit further includes a power feed circuit conductively coupled to the protection circuit and the rectifying circuit. This power feed circuit is operable to separate and pass the received data signal to a network physical layer and separate and pass the received power signal to a power management module.

Abstract: A converter or a resampler used in a digital communication system converts a first digital signal representing an analog signal into a second digital signal representing the same analog signal. The converter includes a converter filter and a timing circuit. The timing circuit provides a first clock generated from a second clock, and a phase control signal for controlling the conversion of the converter filter. The timing circuit is preferably a numerical controlled oscillator (NCO) and includes an accumulator for generating the first clock from the second clock and a phase offset, and a phase calculator which receives the phase offset to generate a phase control signal. The phase control signal includes a plurality of phase weighting signals, a plurality of control signals, and an interpolation signal. The first digital signal is selectively convoluted with the phase weighting signals, which is controlled by the control signals.

Abstract: An adaptive filter is provided which has fixed point or floating point data stored in a data RAM (74) and block scale floating point coefficients stored in a coefficient RAM (84). The data and coefficients are utilized in a filter algorithm which utilizes a multiplier and an accumulator to provide a convolution result. Coefficients are updated by adding the multiplied result of the data RAM value and the error value to the old value of the coefficient. This is done for all the coefficient values in the coefficient RAM. The error value indicates the difference between the filter output and the sampled near-end signal that is the echo. These new coefficients are examined and if any have a value above or all have a value below a predetermined threshold, then the mantissas of all the coefficients are shifted and the exponent adjusted in the next filter cycle.