Patents by Inventor John Charles Desko

John Charles Desko has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6987052
    Abstract: A method of forming a semiconductor structure in a semiconductor wafer includes the steps of forming an epitaxial layer on at least a portion of a semiconductor substrate of a first conductivity type and forming at least one trench through the epitaxial layer to at least partially expose the substrate. The method further includes doping at least one or more sidewalls of the at least one trench with an impurity of a known concentration level. The at least one trench is then substantially filled with a filler material. In this manner, a low-resistance electrical path is formed between an upper surface of the epitaxial layer and the substrate.
    Type: Grant
    Filed: October 30, 2003
    Date of Patent: January 17, 2006
    Assignee: Agere Systems Inc.
    Inventors: Frank A. Baiocchi, John Charles Desko, Bailey R. Jones, Sean Lian
  • Patent number: 6790753
    Abstract: A Schottky diode is fabricated by a sequence of fabrication by a sequence of fabrication steps. An active region of a semiconductor substrate is defined in which a Schottky diode is fabricated. At least first and second layers of insulating material are applied over the active area. A first layer of insulating material, having a first etching rate, is applied over the active area. A second layer of insulating material having a second, greater, etch rate is applied over the first layer of insulating material to a thickness that is about twice the thickness of the first layer of insulating material. The insulating material is patterned and a window is etched through the layers of insulating material to the semiconductor substrate. Metal is applied and unwanted metal is etched away leaving metal in the window forming a Schottky contact therein. One or more barrier layers may be employed.
    Type: Grant
    Filed: October 29, 2003
    Date of Patent: September 14, 2004
    Assignee: Agere Systems Inc
    Inventors: John Charles Desko, Michael J Evans, Chung-Ming Hsieh, Tzu-Yen Hsieh, Bailey R Jones, Thomas J. Krutsick, John Michael Siket, Jr., Brian Eric Thompson, Steven W. Wallace
  • Publication number: 20040089908
    Abstract: A Schottky diode is fabricated by a sequence of fabrication by a sequence of fabrication steps. An active region of a semiconductor substrate is defined in which a Schottky diode is fabricated. At least first and second layers of insulating material are applied over the active area. A first layer of insulating material, having a first etching rate, is applied over the active area. A second layer of insulating material having a second, greater, etch rate is applied over the first layer of insulating material to a thickness that is about twice the thickness of the first layer of insulating material. The insulating material is patterned and a window is etched through the layers of insulating material to the semiconductor substrate. Metal is applied and unwanted metal is etched away leaving metal in the window forming a Schottky contact therein. One or more barrier layers may be employed.
    Type: Application
    Filed: October 29, 2003
    Publication date: May 13, 2004
    Inventors: John Charles Desko, Michael J. Evans, Chung-Ming Hsieh, Tzu-Yen Hsieh, Bailey R. Jones, Thomas J. Krutsick, John Michael Siket, Brian Eric Thompson, Steven W. Wallace
  • Patent number: 6690037
    Abstract: A Schottky diode is fabricated by a sequence of fabrication by a sequence of fabrication steps. An active region of a semiconductor substrate is defined in which a Schottky diode is fabricated. At least first and second layers of insulating material are applied over the active area. A first layer of insulating material, having a first etching rate, is applied over the active area. A second layer of insulating material having a second, greater, etch rate is applied over the first layer of insulating material to a thickness that is about twice the thickness of the first layer of insulating material. The insulating material is patterned and a window is etched through the layers of insulating material to the semiconductor substrate. Metal is applied and unwanted metal is etched away leaving metal in the window forming a Schottky contact therein. One or more barrier layers may be employed.
    Type: Grant
    Filed: August 31, 2000
    Date of Patent: February 10, 2004
    Assignee: Agere Systems Inc.
    Inventors: John Charles Desko, Michael J Evans, Chung-Ming Hsieh, Tzu-Yen Hsieh, Bailey R Jones, Thomas J. Krutsick, John Michael Siket, Jr., Brian Eric Thompson, Steven W. Wallace
  • Patent number: 6372600
    Abstract: There is described a method of making a bonded wafer by diffusing regions of a first wafer proximate a first major surface. Trenches are etched a predetermined distance into the first wafer from the first major surface toward a second major surface. The first major surface and trenches are coated with oxide. The first major surface of the first wafer is bonded to a second wafer to form a bonded wafer. The second major surface of the bonded wafer which is also the second major surface of the first wafer is ablated until oxide in the trenches is detected. The bonded wafer is cut into chips which are packaged as integrated circuits.
    Type: Grant
    Filed: August 30, 1999
    Date of Patent: April 16, 2002
    Assignee: Agere Systems Guardian Corp.
    Inventors: John Charles Desko, Muhammed Ayman Shibib