Abstract: System and method of a pace engine for governing the different transmission rates tailored for different connections by rate pacing a plurality of queues are described. Roughly described, the pace engine includes a binning controller for receiving queues from a transmit DMA queue manager and determines the earliest allowed time for a particular queue that is stored and paced in a Work Bin, a Fast Bin, or a Slow Bin. A pace table stores information about the minimum inter-packet-gap for each connection that is coupled to the transmit DMA queue manager. A timer is coupled to the binning controller with a multi-bit continuous counter that increments at a predetermined time unit and wraps around after a predetermined amount of time.

Abstract: A system includes an interface, a synchronization module, a pre-filtering module and a data alignment module. The interface is configured to connect a first device having a first transfer rate and a second device having a second transfer rate. The interface transfers a data stream from the first device to the second device. The synchronization module is provided within the second device and is configured to synchronize the first transfer rate and the second transfer rate. The pre-filtering module is connected to the synchronization module, and the pre-filtering module is configured to mask a non-compliant input within the data stream into a compliant output. The data alignment module is connected to the pre-filtering module, and the data alignment module is configured to perform logic computations on the legal output.

Abstract: Roughly described, a network interface device is assigned a maximum extent-of-search. A hash function is applied to the header information of each incoming packet, to generate a hash code for the packet. The hash code designates a particular subset of the table within which the particular header information should be found, and an iterative search is made within that subset. If the search locates a matching entry before the search limit is exceeded, then the incoming data packet is delivered to the receive queue identified in the matching entry. But if the search reaches the search limit before a matching entry is located, then device delivers the packet to a default queue, such as a kernel queue, in the host computer system. The kernel is then responsible for delivering the packet to the correct endpoint.

Abstract: Method and apparatus for retrieving buffer descriptors from a host memory for use by a peripheral device. In an embodiment, a peripheral device such as a NIC includes a plurality of buffer descriptor caches each corresponding to a respective one of a plurality of host memory descriptor queues, and a plurality of queue descriptors each corresponding to a respective one of the host memory descriptor queues. Each of the queue descriptors includes a host memory read address pointer for the corresponding descriptor queue, and this same read pointer is used to derive algorithmically the descriptor cache write addresses at which to write buffer descriptors retrieved from the corresponding host memory descriptor queue.

Abstract: Method for managing a data transmit queue, for use with a host and a network interface device. Roughly described, the host writes data buffer descriptors into a transmit descriptor queue, and the network interface device writes events to notify the host when it has completed processing of a transmit data buffer. Each of the transmit completion event descriptors notify the host of completion of a plurality of the transmit data buffers.

Abstract: A method for selectively deskewing data traveling through a bus in a network device is disclosed. Bit-level data is received from each data line of a plurality of data lines of the bus. Vertical line information is detected for the plurality of data lines to determine if there is a match with a training pattern. A skew distance is calculated once there is a match with the training pattern. Then, the plurality of data lines are bit aligned based on the skew distance.

Abstract: The invention provides a novel method of data processing in a multiport communication system having a decision making engine for controlling data forwarding between the receive ports and at least one transmit port. Data blocks representing received data packets are placed in data queues corresponding to the receive ports. The data queues are transferred one at a time in successive time slots to logic circuitry that determines the transmit ports. The time slots are dynamically allocated to the data queues in accordance with data traffic at the corresponding receive ports.

Abstract: A novel system and method of automatically detecting a change in network node connection in a multiport data switching system having receive ports for receiving data packets from network nodes, and a decision making engine for controlling data forwarding. Data blocks representing received data packets are placed in data queues corresponding to the receive ports. The data queues are transferred to logic circuitry for processing in accordance with a predetermined algorithm. This processing includes automatically detecting a change in connection between at least one of the network nodes and at least one of the receive ports, based on a search of an address table having address information relating to the receive ports. The address table may be searched for an address entry having a source address and VLAN address information that match a source address and VLAN address information of the received data packet.

Abstract: A novel method of providing an external host processor with access to registers located in different clock domains. The method comprises the steps of translating host processor interface signals into internal register interface signals, and performing handshaking with the registers via the internal register interface. The handshaking includes supplying registers with a register access signal for enabling access to a selected register, and producing a register ready signal in response to the register access signal. Synchronization signals delayed with respect to the register ready signal may be used for synchronizing registers located in different clock domains with the processor interface.

Abstract: A novel method is provided for initializing a data processing system having registers programmable with configuration data read from a non-volatile memory at power-up. The method includes segmenting the non-volatile memory into a first portion for storing first data, and a second portion for storing second data having lower priority than the first data. The first portion is smaller than the second portion. The first data are read from the first portion to program a first group of registers. Thereafter, the second data are read from the second portion to program a second group of registers. As a result, a host is enabled to access the first group of registers, while the second data are being read from the second memory portion.

Abstract: A method for managing business information by a first business entity using a server system is provided. The server system is coupled to a centralized database and at least one client system. The method includes receiving at the server system business information relating to at least one second business entity through the client system, calculating business information based on the business information previously entered through the client system, generating a plurality of reports based on the business information, validating the business information contained in the reports, and storing the business information and the generated reports in the centralized database.

Abstract: A network switch configured for switching data packets across multiple ports uses an external memory to store data frames. A scheduler controls access to the external memory based on predetermined arbitration logic. When a data frame is transmitted to the external memory, a portion of the data frame is stored on the switch for processing by decision making logic to generate frame forwarding information. The data frame is then transmitted back to the switch for transmission through the appropriate port(s) on the switch.

Abstract: A network interface device includes a random access memory used as a transmit and receive buffer for transmission and reception of data frames between a host computer bus and a packet switched network. The network interface device includes read and write controllers for each of the transmit and receive buffers, where each write controller operates in a clock domain separate from the corresponding read controller. Read and write counters are each implemented as gray code counters that increment a corresponding pointer value by changing a single bit. A synchronization circuit selectively sets a full or empty flag based on an asynchronous comparison of the read and write pointer values. Use of gray code counters for the read pointer value and write pointer value ensures accurate comparisons in a multi-clock environment.

Abstract: A method and apparatus are disclosed for decreasing the amount of time required to initialize a multiport switch. An address table stores addresses of source and destination stations that transmit and receive data frames to and from the multiport switch. Initialization logic is used for constructing and initializing the address table upon startup of the multiport switch. During normal operation of the multiport switch, a scheduler functions to allocate address table access bandwidth to various components of the multiport switch. Upon startup of the multiport switch, the scheduler increases the amount of bandwidth allocated to the initialization logic. The amount of bandwidth allocated to the initialization logic is decreased once the multiport switch is initialized.

Abstract: A network interface has a static random access memory (SRAM) that outputs ordered data to a target by using a first and second holding register, and an output holding register. The SRAM supplies a data set to the first holding register which supplies the first data set to the second holding register. The SRAM also replenishes the first holding register with a second data set. A multiplexer selectively supplies the data set stored in one of the two holding registers to the output holding register which supplies that data set to a bus connected to the target. A bus interface unit state machine supplies a select signal to the multiplexer to control the selection between the first and second holding registers. The state machine generates the select signal based on a bus access controller detecting a target ready signal generated by the target indicating the target's readiness to receive a data set. The select signal enables the multiplexer to supply the next ordered data set to the output holding register.

Abstract: A saddle anchorage in which the direction of the prestress is not perpendicular to the compression surface of the concrete structure. The anchorage comprises a saddle including a rectangular metal plate provided with two parallel locking portions defining a hollow portion therebetween, a bottom portion for the hollow portion, a first rib plate, a second rib plate, a third rib plate having a first opening, a hollow cylindrical sleeve, a plurality of U-shaped first reinforcing steel bars, and a plurality of U-shaped second reinforcing steel bars; and a rider for fixing an anchor head including two triangular side plates provided with locking portions, a rectangular top plate, and a front plate having a second opening.

Abstract: A doll having a heads torso and limbs e.g., a pair of arms and a pair of legs. Each pair of limbs is in the form of a unitary elongated member of a fixed length which are movably, e.g., slidably, mounted with respect to the torso so that each of the limbs extend out of the torso. The length that each limb extends out of the torso is adjustable so that an increase in the distance that one limb extends out of the torso correspondingly decreases the length that the other limb extends out of the torso and vice-versa.