Abstract: A smart card that allows for the categorization of expenses at the time they are incurred and the automatic generation and storage of information concerning the date, payee, and amount of the transaction. A single smart card is utilized to record and categorize transactions as they occur by transaction identities. These transaction identities are business or personal classification, cash, check, or credit card type transactions, and expense categories. The smart card has a alphanumeric display and a keyboard for selecting the class, type, and category. These items are selected by the entry of numbers on the keyboard but textual information is displayed to identify these items in response to the entered numbers. A program in a personal computer is used to specify the class, type, and categories along with the textual information in the smart card via a smart card reader. These specifications correspond to a spreadsheet that has been entered on the personal computer by the user of the smart card.

Abstract: A ROM patching facility is disclosed which permits any ROM address location containing defective information to be patched. New and updated program information is supplied to the system upon the detection of each address word that is to be patched. The disclosed equipment repatches one or more times a ROM address that has already been patched. Upon the detection of each such address, the program information associated with the most recent implemented patch is returned to the system. The disclosed equipment comprises a plurality of PROM decoders for detecting ROM addresses that are to be patched and for generating output signals representing each patched address, encoders for receiving the decoder output signals and for encoding each such signal into binary address information, and auxiliary memories controlled by the encoder address information for providing valid program information to the system upon each detection of a patched ROM address.

Abstract: A read only memory (ROM) patching arrangement is disclosed which provides valid output information whenever ROM locations containing invalid information are addressed. The disclosed arrangement detects the receipt of each ROM address word representing a defective location, temporarily inhibits the output of the ROM, and causes a small auxiliary PROM to output valid information as a substitute for that in the defective ROM location. Decoder circuitry is disclosed which uses a minimum number of small capacity PROMs to detect a limited number of ROM addresses to be patched.

Abstract: A shift and rotate circuit is disclosed for a processor which receives 16-bit words as input data, which breaks down each received word into four 4-bit bytes, and which performs logical and arithmetic operations on each word on a byte-by-byte basis. A word is shifted a specified number of bit positions (1) by entering the word byte-by-byte in consecutive locations of a first 4-bit wide memory, (2) by entering the same word in an ordered byte sequence in a second 4-bit wide memory with the ordered sequence being determined by the number of bit positions the word is to be shifted, and (3) by concurrently applying the contents of both memories byte-by-byte to the shift and rotate circuit which shift the received information to the required number of bit positions and writes the shifted information into consecutive locations of the second memory. The 4-bit bytes of the shifted word are ultimately reconstituted into a 16-bit word and outputted onto the I/O system.

Abstract: A microprogrammed processor which receives 16-bit words as input data from an I/O system, breaks down each received word into four 4-bit bytes, and performs all logical and arithmetic operations on a byte-by-byte basis. The processed bytes may either be stored for further use or reconstituted into 16-bit words and outputted to the I/O system. The processor includes two source buses for applying information to an arithmetic unit (AMU), a destination bus for receiving the AMU output, as well as circuits such as memories and registers for selectively applying AMU input information to the source buses and for receiving AMU output information from the destination bus. Certain ones of the memories can both apply information to source buses and receive information from the destination bus on the same machine operation. Microprogrammed controlled gating facilities specify the circuits that are to be connected to the buses on each machine operation.