Patents by Inventor John Christopher Kriz
John Christopher Kriz has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8598941Abstract: A compensation circuit for controlling a variation in output impedance of at least one buffer circuit includes a monitor circuit and a control circuit coupled with the monitor circuit. The monitor circuit includes a pull-up portion including at least one PMOS transistor and a pull-down portion comprising at least one NMOS transistor. The monitor circuit is configured to track an operation of an output stage of the buffer circuit and is operative to generate at least a first control signal indicative of a status of at least one characteristic of corresponding pull-up and pull-down portions in the output stage of the buffer circuit over variations in PVT conditions to which the buffer circuit may be subjected. The control circuit is operative to generate a set of digital control bits as a function of the first control signal. The set of digital control bits is operative to compensate the pull-up and pull-down portions in the output stage of the buffer circuit over prescribed variations in PVT conditions.Type: GrantFiled: June 21, 2011Date of Patent: December 3, 2013Assignee: LSI CorporationInventors: Dipankar Bhattacharya, Ashish V. Shukla, John Christopher Kriz, Makeshwar Kothandaraman, Pankaj Kumar, Pramod Parameswaran
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Patent number: 8441281Abstract: A differential buffer circuit having increased output voltage swing includes a differential input stage including at least first and second transistors, the first and second transistors being operative to receive first and second signals, respectively. The buffer circuit further includes a bias stage connected between the differential input stage and a first voltage source. The bias stage is operative to generate a quiescent current as a function of a third signal supplied to the bias stage. A load circuit is connected between a second voltage source and the differential input stage, first and second differential outputs of the buffer circuit being generated at a junction between the load circuit and the differential input stage. The load circuit includes first and second switching elements coupled with the first and second transistors, respectively.Type: GrantFiled: June 21, 2011Date of Patent: May 14, 2013Assignee: LSI CorporationInventors: Makeshwar Kothandaraman, Pankaj Kumar, Paul K. Hartley, John Christopher Kriz
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Patent number: 8362803Abstract: A voltage translator circuit includes an input stage adapted for receiving an input signal referenced to a first voltage supply, a first latch circuit adapted for connection with a second voltage supply and operative to at least temporarily store a logic state of the input signal, and a voltage clamp coupled between the input stage and the first latch circuit. The voltage clamp is operative to set a maximum voltage across the input stage to a prescribed level. The voltage translator circuit generates a first output signal at a first output formed at a junction between the first latch circuit and the voltage clamp. A second latch circuit is connected to the first output in a feedback configuration. The second latch circuit is operative to retain a logical state of the first output signal as a function of at least a first control signal supplied to the second latch circuit regardless of a state of the first voltage supply.Type: GrantFiled: February 18, 2011Date of Patent: January 29, 2013Assignee: LSI CorporationInventors: Peter J. Nicholas, John Christopher Kriz, Dipankar Bhattacharya, James John Bradley
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Publication number: 20120326768Abstract: A compensation circuit for controlling a variation in output impedance of at least one buffer circuit includes a monitor circuit and a control circuit coupled with the monitor circuit. The monitor circuit includes a pull-up portion including at least one PMOS transistor and a pull-down portion comprising at least one NMOS transistor. The monitor circuit is configured to track an operation of an output stage of the buffer circuit and is operative to generate at least a first control signal indicative of a status of at least one characteristic of corresponding pull-up and pull-down portions in the output stage of the buffer circuit over variations in PVT conditions to which the buffer circuit may be subjected. The control circuit is operative to generate a set of digital control bits as a function of the first control signal. The set of digital control bits is operative to compensate the pull-up and pull-down portions in the output stage of the buffer circuit over prescribed variations in PVT conditions.Type: ApplicationFiled: June 21, 2011Publication date: December 27, 2012Applicant: LSI CORPORATIONInventors: Dipankar Bhattacharya, Ashish V. Shukla, John Christopher Kriz, Makeshwar Kothandaraman, Pankaj Kumar, Pramod Parameswaran
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Publication number: 20120326745Abstract: A differential buffer circuit having increased output voltage swing includes a differential input stage including at least first and second transistors, the first and second transistors being operative to receive first and second signals, respectively. The buffer circuit further includes a bias stage connected between the differential input stage and a first voltage source. The bias stage is operative to generate a quiescent current as a function of a third signal supplied to the bias stage. A load circuit is connected between a second voltage source and the differential input stage, first and second differential outputs of the buffer circuit being generated at a junction between the load circuit and the differential input stage. The load circuit includes first and second switching elements coupled with the first and second transistors, respectively.Type: ApplicationFiled: June 21, 2011Publication date: December 27, 2012Applicant: LSI CORPORATIONInventors: Makeshwar Kothandaraman, Pankaj Kumar, Paul K. Hartley, John Christopher Kriz
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Publication number: 20120212256Abstract: A voltage translator circuit includes an input stage adapted for receiving an input signal referenced to a first voltage supply, a first latch circuit adapted for connection with a second voltage supply and operative to at least temporarily store a logic state of the input signal, and a voltage clamp coupled between the input stage and the first latch circuit. The voltage clamp is operative to set a maximum voltage across the input stage to a prescribed level. The voltage translator circuit generates a first output signal at a first output formed at a junction between the first latch circuit and the voltage clamp. A second latch circuit is connected to the first output in a feedback configuration. The second latch circuit is operative to retain a logical state of the first output signal as a function of at least a first control signal supplied to the second latch circuit regardless of a state of the first voltage supply.Type: ApplicationFiled: February 18, 2011Publication date: August 23, 2012Applicant: LSI CorporationInventors: Peter J. Nicholas, John Christopher Kriz, Dipankar Bhattacharya, James John Bradley
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Patent number: 8159262Abstract: A compensation circuit for controlling a variation in output impedance of at least one buffer circuit includes a monitor circuit having a pull-up portion comprising at least one PMOS transistor and a pull-down portion comprising at least one NMOS transistor. The monitor circuit is configured to track an operation of an output stage in the buffer circuit and is operative to generate a first control signal indicating a status of at least one characteristic of corresponding pull-up and pull-down portions in the output stage over variations in PVT conditions to which the buffer circuit may be subjected. The compensation circuit further includes a control circuit generating first and second sets of digital control bits for compensating the pull-up and pull-down portions in the output stage over prescribed variations in PVT conditions. The second set of digital control bits is generated based at least on the first set of digital control bits and the first control signal.Type: GrantFiled: February 18, 2011Date of Patent: April 17, 2012Inventors: Dipankar Bhattacharya, Ashish V. Shukla, John Christopher Kriz, Makeshwar Kothandaraman
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Patent number: 7218169Abstract: A compensation circuit comprises a reference circuit including a reference NMOS device and a reference PMOS device. The reference circuit is operative to generate a first reference signal and a second reference signal, the first reference signal being a function of at least one of a process characteristic, a voltage characteristic and a temperature characteristic of the reference NMOS device, and the second reference signal being a function of at least one of a process characteristic, a voltage characteristic and a temperature characteristic of the reference PMOS device. The compensation circuit further comprises a control circuit connected to the reference circuit.Type: GrantFiled: December 23, 2003Date of Patent: May 15, 2007Assignee: Agere Syatems Inc.Inventors: Dipankar Bhattacharya, Makeshwar Kothandaraman, John Christopher Kriz, Bernard Lee Morris, Jeffrey Jay Nagy, Stefan Allen Siegel
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Patent number: 7106107Abstract: A comparator circuit includes a reference generator connecting to a first source providing a first voltage. The reference generator is operative to generate a reference signal and includes a control circuit selectively operable in at least a first mode or a second mode in response to a first control signal, wherein in the first mode the reference signal is not generated, and in the second mode the reference generator is operative to generate the reference signal. The comparator circuit further includes a comparator connecting to a second source providing a second voltage, the second voltage being less than the first voltage. The comparator is operative to receive the reference signal and an input signal, and to generate an output signal which is a function of a comparison between the input signal and the reference signal.Type: GrantFiled: January 31, 2005Date of Patent: September 12, 2006Assignee: Agere Systems Inc.Inventors: Dipankar Bhattacharya, John Christopher Kriz, Bernard L. Morris, William B. Wilson
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Patent number: 7034653Abstract: A semiconductor resistor comprises a resistor body formed on a semiconductor substrate and first and second conductive terminals electrically connected to the resistor body at opposite ends thereof. The semiconductor resistor further includes at least first and second conductive paths between at least one of the first and second conductive terminals and the resistor body. The at least one conductive terminal is configured such that a resistance of the at least one conductive terminal between the at least first and second conductive paths is substantially matched to a resistance of the resistor body between the at least first and second conductive paths. In this manner, a current distribution between the at least first and second conductive paths is substantially matched.Type: GrantFiled: January 30, 2004Date of Patent: April 25, 2006Assignee: Agere Systems Inc.Inventors: Dipankar Bhattacharya, John Christopher Kriz, Stefan Allen Siegel, Joseph E. Simko, Yehuda Smooha
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Patent number: 6992489Abstract: A circuit configurable for indicating a voltage level of an input signal applied to the circuit includes at least one transistor having a first terminal connected to a first voltage supply, a second terminal configured for receiving the input signal, and a third terminal operatively coupled to an output of the circuit. The circuit further includes a passive load connected between the third terminal of the transistor and a second voltage supply. The circuit is configured to generate an output signal at the output of the circuit. The output signal being at a first value indicates that the input signal is substantially at a first voltage level, and the output signal being at a second value indicates that the input signal is substantially at a second voltage level.Type: GrantFiled: February 11, 2004Date of Patent: January 31, 2006Assignee: Agere Systems Inc.Inventors: Dipankar Bhattacharya, John Christopher Kriz, Joseph E. Simko
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Patent number: 6774698Abstract: An apparatus is disclosed for translating a lower voltage signal, utilized in a low voltage integrated circuit, to a higher voltage signal suitable for use in a high voltage circuit. The apparatus includes a low voltage transistor assembly capable of operating in response to the lower voltage signal; a voltage regulator which is configured to limit an applied voltage across the low voltage transistor assembly; and a high voltage converter which is responsive to the operation of the low voltage transistor assembly to generate the higher voltage signal. The voltage regulator includes a reference voltage generator and a voltage limiter.Type: GrantFiled: January 30, 2003Date of Patent: August 10, 2004Assignee: Agere Systems Inc.Inventors: Dipankar Bhattacharya, Makeshwar Kothandaraman, John Christopher Kriz, Bernard Lee Morris, Stefan Allen Siegel
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Publication number: 20040150454Abstract: An apparatus is disclosed for translating a lower voltage signal, utilized in a low voltage integrated circuit, to a higher voltage signal suitable for use in a high voltage circuit. The apparatus includes a low voltage transistor assembly capable of operating in response to the lower voltage signal; a voltage regulator which is configured to limit an applied voltage across the low voltage transistor assembly; and a high voltage converter which is responsive to the operation of the low voltage transistor assembly to generate the higher voltage signal. The voltage regulator includes a reference voltage generator and a voltage limiter.Type: ApplicationFiled: January 30, 2003Publication date: August 5, 2004Inventors: Dipankar Bhattacharya, Makeshwar Kothandaraman, John Christopher Kriz, Bernard Lee Morris, Stefan Allen Siegel