Patents by Inventor John D. Cayo

John D. Cayo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Verification of photonic integrated circuits
    Patent number: 10929590
    Abstract: Techniques and mechanisms for the use of layout-versus-schematic (LVS) design tools to validate photonic integrated circuit designs. Various implementations employ alternate analysis techniques with LVS analysis tools to perform one or more LVS analysis processes on photonic integrated circuits. These analysis processes may include curvilinear design validation and the associated flow implementations.
    Type: Grant
    Filed: December 12, 2018
    Date of Patent: February 23, 2021
    Assignee: Mentor Graphics Corporation
    Inventors: Ruping Cao, John G. Ferguson, John D. Cayo, Alexandre Arriordaz
  • VERIFICATION OF PHOTONIC INTEGRATED CIRCUITS
    Publication number: 20190114384
    Abstract: Techniques and mechanisms for the use of layout-versus-schematic (LVS) design tools to validate photonic integrated circuit designs. Various implementations employ alternate analysis techniques with LVS analysis tools to perform one or more LVS analysis processes on photonic integrated circuits. These analysis processes may include curvilinear design validation and the associated flow implementations.
    Type: Application
    Filed: December 12, 2018
    Publication date: April 18, 2019
    Inventors: Ruping Cao, John G. Ferguson, John D. Cayo, Alexandre Arriordaz
  • Verification of photonic integrated circuits
    Patent number: 10185799
    Abstract: Techniques and mechanisms for the use of layout-versus-schematic (LVS) design tools to validate photonic integrated circuit designs. Various implementations employ alternate analysis techniques with LVS analysis tools to perform one or more LVS analysis processes on photonic integrated circuits. These analysis processes may include curvilinear design validation and the associated flow implementations.
    Type: Grant
    Filed: April 22, 2015
    Date of Patent: January 22, 2019
    Assignee: Mentor Graphics Corporation
    Inventors: Ruping Cao, John G. Ferguson, John D. Cayo, Alexandre Arriordaz
  • Verification Of Photonic Integrated Circuits
    Publication number: 20160055289
    Abstract: Techniques and mechanisms for the use of layout-versus-schematic (LVS) design tools to validate photonic integrated circuit designs. Various implementations employ alternate analysis techniques with LVS analysis tools to perform one or more LVS analysis processes on photonic integrated circuits. These analysis processes may include curvilinear design validation and the associated flow implementations.
    Type: Application
    Filed: April 22, 2015
    Publication date: February 25, 2016
    Inventors: Ruping Cao, John G. Ferguson, John D. Cayo, Alexandre Arriordaz