Patents by Inventor John D. Flanagan
John D. Flanagan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20240165724Abstract: The present application provides an electrical discharge machining system for drilling a hole in a workpiece using a flushing fluid. The electrical discharge machining system may include an electrode with the electrode positioned in an electrode guide, and an integrated external flushing system. The integrated external flushing system may include a guide cap and a concentric flushing channel defined between the guide cap and the electrode guide so as to allow the flushing fluid to remain attached to the electrode guide.Type: ApplicationFiled: November 22, 2022Publication date: May 23, 2024Inventors: James Scott FLANAGAN, Weston Michael SUCHENSKI, John D. PITTARD
-
Publication number: 20240112794Abstract: Provided is a system configured to allocate healthcare resources for population health management using time values, health scores, or health condition labels stored in a population of records.Type: ApplicationFiled: October 12, 2023Publication date: April 4, 2024Inventors: John D. Golenski, David J. Flanagan
-
Patent number: 7596734Abstract: A system for performing AC self-test on an integrated circuit that includes a system clock for normal operation is provided. The system includes the system clock, self-test circuitry, a first and second test register to capture and launch test data in response to a sequence of data pulses, and a logic circuit to be tested. The self-test circuitry includes an AC self-test controller and a clock splitter. The clock splitter generates the sequence of data pulses including a long data capture pulse followed by an at speed data launch pulse and an at speed data capture pulse followed by a long data launch pulse. The at speed data launch pulse and the at speed data capture pulse are generated for a common cycle of the system clock.Type: GrantFiled: August 4, 2008Date of Patent: September 29, 2009Assignee: International Business Machines CorporationInventors: John D. Flanagan, Jay R. Herring, Tin-Chee Lo
-
Publication number: 20080313514Abstract: A system for performing AC self-test on an integrated circuit that includes a system clock for normal operation is provided. The system includes the system clock, self-test circuitry, a first and second test register to capture and launch test data in response to a sequence of data pulses, and a logic circuit to be tested. The self-test circuitry includes an AC self-test controller and a clock splitter. The clock splitter generates the sequence of data pulses including a long data capture pulse followed by an at speed data launch pulse and an at speed data capture pulse followed by a long data launch pulse. The at speed data launch pulse and the at speed data capture pulse are generated for a common cycle of the system clock.Type: ApplicationFiled: August 4, 2008Publication date: December 18, 2008Applicant: International Business Machines CorporationInventors: John D. Flanagan, Jay R. Herring, Tin-Chee Lo
-
Patent number: 7430698Abstract: A method and system for performing AC self-test on an integrated circuit that includes a system clock for use during normal operation are provided. The method includes applying a long data capture pulse to a first test register in response to the system clock, applying an at speed data launch pulse to the first test register in response to the system clock, inputting the data from the first register to a logic path in response to applying the at speed data launch pulse to the first test register, applying an at speed data capture pulse to a second test register in response to the system clock, inputting the logic path output to the second test register in response to applying the at speed data capture pulse to the second test register, and applying a long data launch pulse to the second test register in response to the system clock.Type: GrantFiled: December 30, 2005Date of Patent: September 30, 2008Assignee: International Business Machines CorporationInventors: John D. Flanagan, Jay R. Herring, Tin-Chee Lo
-
Patent number: 7058866Abstract: A method for performing AC self-test on an integrated circuit, including a system clock for use during normal operation. The method includes applying a long data capture pulse to a first test register in response to the system clock, and further applying at an speed data launch pulse to the first test register in response to the system clock. Inputting the data from the first register to a logic path in response to applying the at speed data launch pulse to the first test register. Applying at speed data capture pulse to a second test register in response to the system clock. Inputting the output from the logic path to the second test register in response to applying the at speed data capture pulse to the second register. Applying a long data launch pulse to the second test register in response to the system clock.Type: GrantFiled: April 24, 2002Date of Patent: June 6, 2006Assignee: International Business Machines CorporationInventors: John D. Flanagan, Jay R. Herring, Tin-Chee Lo
-
Patent number: 6738921Abstract: A clock controller and clock generating method are provided for AC self-test timing analysis of a logic system. The controller includes latch circuitry which receives a DC input signal at a data input, and a pair of continuous out-of-phase clock signals at capture and launch clock inputs thereof. The latch circuitry outputs two overlapping pulses responsive to the DC input signal going high. The two overlapping pulses are provided to waveform shaper circuitry which produces therefrom two non-overlapping pulses at clock speed of the logic system to be tested. The two non-overlapping pulses are a single pair of clock pulses which facilitate AC self-test timing analysis of the logic system.Type: GrantFiled: March 20, 2001Date of Patent: May 18, 2004Assignee: International Business Machines CorporationInventors: Tinchee Lo, John D. Flanagan
-
Publication number: 20030204800Abstract: An exemplary embodiment of the present invention is a method for performing AC self-test on an integrated circuit that includes a system clock for use during normal operation. The method comprises applying a long data capture pulse to a first test register in response to said system clock. An at speed data launch pulse is applied to the first test register in response to said system clock. The data from the first register is input to a logic path in response to applying the at speed data launch pulse to the first test register. An at speed data capture pulse is applied to a second test register in response to the system clock. The output from the logic path is input to the second test register in response to applying the at speed data capture pulse to the second test register. A long data launch pulse is applied to the second test register in response to the system clock. An additional embodiment includes a system for performing AC self-test on an integrated circuit that includes a system clock.Type: ApplicationFiled: April 24, 2002Publication date: October 30, 2003Applicant: International Business Machines CorporationInventors: John D. Flanagan, Jay R. Herring, Tin-Chee Lo
-
Publication number: 20020138157Abstract: A clock controller and clock generating method are provided for AC self-test timing analysis of a logic system. The controller includes latch circuitry which receives a DC input signal at a data input, and a pair of continuous out-of-phase clock signals at capture and launch clock inputs thereof. The latch circuitry outputs two overlapping pulses responsive to the DC input signal going high. The two overlapping pulses are provided to waveform shaper circuitry which produces therefrom two non-overlapping pulses at clock speed of the logic system to be tested. The two non-overlapping pulses are a single pair of clock pulses which facilitate AC self-test timing analysis of the logic system.Type: ApplicationFiled: March 20, 2001Publication date: September 26, 2002Applicant: International Business Machines CorporationInventors: Tinchee Lo, John D. Flanagan
-
Patent number: 4686212Abstract: Compositions are provided for the preparation of stable sodium aspirin tablets. The compositions comprise dry, crystalline sodium aspirin, an anhydrous binder that is unreactive to sodium aspirin and a hydrogenated animal or vegetable oil lubricant but lack the traditional tablet disintegrant. Tablets produced from these compositions can be stored for prolonged periods of time yet disintegrate in water at a rate comparable to that of ordinary aspirin.Type: GrantFiled: August 13, 1985Date of Patent: August 11, 1987Assignee: PharmaControl Corp.Inventors: Fred P. Ducatman, John D. Flanagan