Patents by Inventor John D. Gillis

John D. Gillis has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9230725
    Abstract: Embodiments are provided that include methods of designing an inductor. The inductor can include a conductive line including at least one turn and an opening positioned within an interior of a region of the conductive line. Embodiments of forming the inductor can include: providing an inductor design including a conductive line having at least one turn; determining a region of the conductive line that has current density below a threshold; and forming an opening in the region, the opening enclosed within the conductive line.
    Type: Grant
    Filed: February 24, 2012
    Date of Patent: January 5, 2016
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Mete Erturk, John D. Gillis, Casey J. Grant, David Scagnelli, Anthony K. Stamper
  • Publication number: 20120151748
    Abstract: Embodiments disclosed include methods of designing an inductor. The inductor can include a conductive line including at least one turn and an opening positioned within an interior of a region of the conductive line.
    Type: Application
    Filed: February 24, 2012
    Publication date: June 21, 2012
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Mete Erturk, John D. Gillis, Casey J. Grant, David Scagnelli, Anthony K. Stamper
  • Patent number: 8193893
    Abstract: Embodiments of an inductor including a conductive line including at least one turn and an opening positioned within an interior of a region of the conductive line are disclosed. Embodiments of a related method of designing the inductor are also disclosed.
    Type: Grant
    Filed: March 26, 2008
    Date of Patent: June 5, 2012
    Assignee: International Business Machines Corporation
    Inventors: Mete Erturk, John D. Gillis, Casey J. Grant, David Scagnelli, Anthony K. Stamper
  • Patent number: 8169055
    Abstract: At least one through-substrate via is formed around the periphery of a semiconductor chip or a semiconductor chiplet included in a semiconductor chip. The at least one through-substrate via may be a single through-substrate via that laterally surrounds the semiconductor chip or the semiconductor chiplet, or may comprise a plurality of through-substrate vias that surrounds the periphery with at least one gap among the through-substrate vias. A stack of back-end-of-line (BEOL) metal structures that laterally surrounds the semiconductor chip or the semiconductor chiplet are formed directly on the substrate contact vias and electrically connected to the at least one through-substrate via. A metallic layer is formed on the backside of the semiconductor substrate including the at least one through-substrate via. The conductive structure including the metallic layer, the at least one through-substrate via, and the stack of the BEOL metal structures function as an electrical ground built into the semiconductor chip.
    Type: Grant
    Filed: December 10, 2009
    Date of Patent: May 1, 2012
    Assignee: International Business Machines Corporation
    Inventors: John D. Gillis, Wan Ni
  • Publication number: 20100237472
    Abstract: At least one through-substrate via is formed around the periphery of a semiconductor chip or a semiconductor chiplet included in a semiconductor chip. The at least one through-substrate via may be a single through-substrate via that laterally surrounds the semiconductor chip or the semiconductor chiplet, or may comprise a plurality of through-substrate vias that surrounds the periphery with at least one gap among the through-substrate vias. A stack of back-end-of-line (BEOL) metal structures that laterally surrounds the semiconductor chip or the semiconductor chiplet are formed directly on the substrate contact vias and electrically connected to the at least one through-substrate via. A metallic layer is formed on the backside of the semiconductor substrate including the at least one through-substrate via. The conductive structure including the metallic layer, the at least one through-substrate via, and the stack of the BEOL metal structures function as an electrical ground built into the semiconductor chip.
    Type: Application
    Filed: December 10, 2009
    Publication date: September 23, 2010
    Applicant: International Business Machines Corporation
    Inventors: John D. Gillis, Wan Ni
  • Publication number: 20090243778
    Abstract: Embodiments of an inductor including a conductive line including at least one turn and an opening positioned within an interior of a region of the conductive line are disclosed. Embodiments of a related method of designing the inductor are also disclosed.
    Type: Application
    Filed: March 26, 2008
    Publication date: October 1, 2009
    Inventors: Mete Erturk, John D. Gillis, Casey J. Grant, David Scagnelli, Anthony K. Stamper
  • Patent number: 6711392
    Abstract: A balanced power amplifier for radio frequencies. The power amplifier may be switched from operating in a saturation mode, so that AMPS-type radio telephone signals may be optimally amplified, to a linear mode so that CDMA signals may be amplified. A directional coupler splits an input signal into quadrature signal components which are supplied to the input of a pair of dual mode power amplifiers. The output signals from the dual mode amplifiers are recombined in a directional coupler. The directional coupler effectively applies all of the output power to an antenna connected to one of the coupler ports, and effectively isolates the output stages of the amplifiers from any reflected power generated by the antenna.
    Type: Grant
    Filed: June 30, 2000
    Date of Patent: March 23, 2004
    Assignee: International Business Machines Corporation
    Inventor: John D. Gillis