Abstract: The present invention relates to a colostomy appliance with a flushable insert that can be removed and replaced without removing the outer bag, allowing for quicker, easier, and more sanitary disposal of fecal waste. The appliance is comprised of a faceplate with an attachment ring that has a lip and a catch, an outer colostomy bag with top and bottom openings that can be temporarily closed, and an insert made of a flushable material. The insert has an opening that fits over the attachment ring and is aligned and secured in its proper position inside the bag by the lip and the catch of the attachment ring. The present invention also provides a method for using the flushable insert with a colostomy appliance.

Abstract: A circuit for alternately providing a first frequency to a receiver stage (20) and a second frequency to a transmitter stage (25) of a transmitter and receive circuit (11). The circuit comprises an oscillator (38), a first switch (33), a second switch (42), and a control circuit (29). The first switch (33) couples information to the oscillator (38) to be transposed on the second frequency during transmission. The second switch (42) couples the oscillator (38) to either the transmitter stage (25) or the receiver stage (20). Prior to changing oscillator frequency the control circuit (29) disables both outputs of the second switch (42). The control circuit (29) alternately tunes the oscillator (38) to the first frequency and enables the second switch (42) such that the oscillator (38) is coupled to the receiver stage (20) and tunes the oscillator (38) to the second frequency, enables the first switch (33), and enables the second switch (42 ) such that the oscillator (38) is coupled to the transmitter stage (25).

Abstract: A synthesizer is placed in standby mode when a standby portion of a control register is set. Once standby is activated, any detectors and counters are inhibited. The inputs and outputs are reconfigured so as to minimize current drain and to stabilize the VCO control voltage. Recovery from standby is accomplished in two phases. The first phase is started by the receipt of a terminate standby signal. This enables the inputs and starts the counters. The second phase is activated when a signal is received from a feedback counter indicating it has completed a cycle. This causes the preset data to be loaded into the reference counter. The counters are then synchronized; the detector is initialized; and the detector output is enabled. The device also controls an output lock detector and reference frequency signal during the standby mode. The system is also compatible with variable modulus prescalers.

Abstract: A frequency generator in which the PLL frequency synthesizer and the VCO are directly modulated by an input serial data stream for providing an FSK modulated RF output signal useful in narrowband data communication systems. The serial data stream may alternatively modulate either the PLL frequency synthesizer or the VCO alone.

Abstract: A digital phase and frequency detector is capable of providing a linearized transfer function. The digital phase and frequency detector includes two latches each receiving an input and each providing an output. The output of the latches is combined by a logic gate to generate a reset signal. The linearization is a result of providing a delay to the reset signal. The reset signal is used to reset the two latches within the phase and frequency comparator. This improved phase and frequency comparator eliminates non-linearities which would otherwise be inherent in its transfer function and thereby degrade performance of phase-locked systems employing the comparator. The phase and frequency detector is easily manufactured as an integrated circuit and does not require any external signals in order to eliminate the non-linear region.

Abstract: A method of using a sample and hold circuit to obtain a substantially ripple free voltage on the holding capacitor is provided by holding the charge capacitor at a constant voltage during the sampling time and by not routinely charging the charge capacitor to the maximum potential available. This provides a virtually constant voltage from which the holding capacitor can be charged. The level to which the charging capacitor is charged is controlled by an error signal. This error signal is reflected onto the holding capacitor, and is used as an output for the sample and hold circuit.