Patents by Inventor John D. Prymak
John D. Prymak has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 8760848Abstract: A capacitor assembly with a substrate having a first face and a second face. A multiplicity of capacitors are mounted on the first face wherein each capacitor has a first lead and a second lead of opposite polarity to the first lead. A bridge is in electrical contact with multiple first leads. A tree is in electrical contact with the bridge wherein the tree passes through a via of the substrate and is in electrical contact with a first trace of the second face. A second trace is on the second face wherein the second lead is in electrical contact with the second trace.Type: GrantFiled: December 9, 2011Date of Patent: June 24, 2014Assignee: Kemet Electronics CorporationInventors: John D. Prymak, Peter Par Blais, George Haddox, Michael Prevallet, Jim Piller, Chris Stolarski, Chris Wayne
-
Patent number: 8717774Abstract: A capacitive interposer, electronic package having the capacitive interposer and electronic device with the electronic package is described. The interposer has a first planar face and a second planar face. An array of upper connections is on the first planar face and opposing lower connections are on the second planar face with conduction paths between each upper connection of the upper connections and a lower connection of the lower connections. At least one power feed-through capacitor is provided. The capacitor is mounted on the first planar face with the first external termination in direct electrical contact with a first upper connection and the second external termination is in direct electrical contact with a second upper connection. At least one upper connection, first external termination and second external termination are arranged for direct electrical contact with element contact pads of a common element.Type: GrantFiled: November 9, 2011Date of Patent: May 6, 2014Assignee: Kemet Electronics CorporationInventors: Michael S. Randall, Garry Renner, John D. Prymak, Azizuddin Tajuddin
-
Patent number: 8713770Abstract: A ceramic multilayer surface-mount capacitor with inherent crack mitigation void patterning to channel flex cracks into a safe zone, thereby negating any electrical failures.Type: GrantFiled: June 29, 2011Date of Patent: May 6, 2014Assignee: Kemet Electronics CorporationInventor: John D. Prymak
-
Patent number: 8652920Abstract: A process for forming a laminate with capacitance and the laminate formed thereby. The process includes the steps of providing a substrate and laminating a conductive foil on the substrate wherein the foil has a dielectric. A conductive layer is formed on the dielectric. The conductive foil is treated to electrically isolate a region of conductive foil containing the conductive layer from additional conductive foil. A cathodic conductive couple is made between the conductive layer and a cathode trace and an anodic conductive couple is made between the conductive foil and an anode trace.Type: GrantFiled: March 1, 2012Date of Patent: February 18, 2014Assignee: Kamet Electronics CorporationInventors: John D. Prymak, Chris Stolarski, Alethla Melody, Antony P. Chacko, Gregory J. Dunn
-
Patent number: 8576537Abstract: A ceramic multilayer surface-mount capacitor with inherent crack mitigation void patterning to channel flex cracks into a safe zone, thereby negating any electrical failures.Type: GrantFiled: October 17, 2008Date of Patent: November 5, 2013Assignee: Kemet Electronics CorporationInventor: John D. Prymak
-
Patent number: 8470680Abstract: A process for forming a laminate with capacitance and the laminate formed thereby. The process includes the steps of providing a substrate and laminating a conductive foil on the substrate wherein the foil has a dielectric. A conductive layer is formed on the dielectric. The conductive foil is treated to electrically isolate a region of conductive foil containing the conductive layer from additional conductive foil. A cathodic conductive couple is made between the conductive layer and a cathode trace and an anodic conductive couple is made between the conductive foil and an anode trace.Type: GrantFiled: July 28, 2008Date of Patent: June 25, 2013Assignees: Kemet Electronics Corporation, Motorola, Inc.Inventors: John D. Prymak, Chris Stolarski, Alethia Melody, Antony P. Chacko, Gregory J. Dunn
-
Patent number: 8410536Abstract: A process for forming a laminate with capacitance and the laminate formed thereby. The process includes the steps of providing a substrate and laminating a conductive foil on the substrate wherein the foil has a dielectric. A conductive layer is formed on the dielectric. The conductive foil is treated to electrically isolate a region of conductive foil containing the conductive layer from additional conductive foil. A cathodic conductive couple is made between the conductive layer and a cathode trace and an anodic conductive couple is made between the conductive foil and an anode trace.Type: GrantFiled: January 6, 2012Date of Patent: April 2, 2013Assignee: Kemet Electronics CorporationInventors: John D. Prymak, Chris Stolarski, Alethia Melody, Antony P. Chacko, Gregory J. Dunn
-
Publication number: 20120162857Abstract: A process for forming a laminate with capacitance and the laminate formed thereby. The process includes the steps of providing a substrate and laminating a conductive foil on the substrate wherein the foil has a dielectric. A conductive layer is formed on the dielectric. The conductive foil is treated to electrically isolate a region of conductive foil containing the conductive layer from additional conductive foil. A cathodic conductive couple is made between the conductive layer and a cathode trace and an anodic conductive couple is made between the conductive foil and an anode trace.Type: ApplicationFiled: March 1, 2012Publication date: June 28, 2012Inventors: John D. Prymak, Chris Stolarski, Alethla Melody, Antony P. Chacko, Gregory J. Dunn
-
Publication number: 20120106032Abstract: A process for forming a laminate with capacitance and the laminate formed thereby. The process includes the steps of providing a substrate and laminating a conductive foil on the substrate wherein the foil has a dielectric. A conductive layer is formed on the dielectric. The conductive foil is treated to electrically isolate a region of conductive foil containing the conductive layer from additional conductive foil. A cathodic conductive couple is made between the conductive layer and a cathode trace and an anodic conductive couple is made between the conductive foil and an anode trace.Type: ApplicationFiled: January 6, 2012Publication date: May 3, 2012Applicant: Kemet Electronics CorporationInventors: John D. Prymak, Chris Stolarski, Alethia Melody, Anthony P. Chacko, Gregory J. Dunn
-
Publication number: 20120081870Abstract: A capacitive interposer, electronic package having the capacitive interposer and electronic device with the electronic package is described. The interposer has a first planar face and a second planar face. An array of upper connections is on the first planar face and opposing lower connections are on the second planar face with conduction paths between each upper connection of the upper connections and a lower connection of the lower connections. At least one power feed-through capacitor is provided. The capacitor is mounted on the first planar face with the first external termination in direct electrical contact with a first upper connection and the second external termination is in direct electrical contact with a second upper connection. At least one upper connection, first external termination and second external termination are arranged for direct electrical contact with element contact pads of a common element.Type: ApplicationFiled: November 9, 2011Publication date: April 5, 2012Applicant: Kemet Electronics CorporationInventors: Michael S. Randall, Garry Renner, John D. Prymak, Azizuddin Tajuddin
-
Publication number: 20120081834Abstract: A capacitor assembly with a substrate having a first face and a second face. A multiplicity of capacitors are mounted on the first face wherein each capacitor has a first lead and a second lead of opposite polarity to the first lead. A bridge is in electrical contact with multiple first leads. A tree is in electrical contact with the bridge wherein the tree passes through a via of the substrate and is in electrical contact with a first trace of the second face. A second trace is on the second face wherein the second lead is in electrical contact with the second trace.Type: ApplicationFiled: December 9, 2011Publication date: April 5, 2012Applicant: KEMET ELECTRONICS CORPORATIONInventors: John D. Prymak, Peter Par Blais, George Haddox, Michael Prevallet, Jim Piller, Chris Stolarski, Chris Wayne
-
Patent number: 8125766Abstract: A capacitor assembly with a substrate having a first face and a second face. A multiplicity of capacitors are mounted on the first face wherein each capacitor has a first lead and a second lead of opposite polarity to the first lead. A bridge is in electrical contact with multiple first leads. A tree is in electrical contact with the bridge wherein the tree passes through a via of the substrate and is in electrical contact with a first trace of the second face. A second trace is on the second face wherein the second lead is in electrical contact with the second trace.Type: GrantFiled: June 13, 2008Date of Patent: February 28, 2012Assignee: Kemet Electronics CorporationInventors: John D. Prymak, Peter Blais, George Haddox, Michael Prevallet, Jim Piller, Chris Stolarski, Chris Wayne
-
Patent number: 8111524Abstract: A capacitive interposer, electronic package having the capacitive interposer and electronic device with the electronic package is described. The interposer has a first planar face and a second planar face. An array of upper connections is on the first planar face and opposing lower connections are on the second planar face with conduction paths between each upper connection of the upper connections and a lower connection of the lower connections. At least one power feed-through capacitor is provided. The capacitor has a plurality of parallel plates with a dielectric there between. At least one first external termination is in electrical contact with a first set of alternate parallel plates and at least one second external termination is in electrical contact with a second set of alternate parallel plates.Type: GrantFiled: February 12, 2008Date of Patent: February 7, 2012Assignee: Kemet Electronics CorporationInventors: Michael S. Randall, Garry Renner, John D. Prymak, Azizuddin Tajuddin
-
Publication number: 20120019979Abstract: An anode with a pellet wherein the pellet has a bottom surface. The anode further also has an anode wire with a primary axis and extending beyond the pellet along the primary axis wherein the anode wire has a cross-section perpendicular to the primary axis wherein the cross-section of the anode wire breaches the bottom surface.Type: ApplicationFiled: September 30, 2011Publication date: January 26, 2012Applicant: Kemet Electronics CorporationInventor: John D. Prymak
-
Publication number: 20110252614Abstract: A ceramic multilayer surface-mount capacitor with inherent crack mitigation void patterning to channel flex cracks into a safe zone, thereby negating any electrical failures.Type: ApplicationFiled: June 29, 2011Publication date: October 20, 2011Applicant: Kemet Electronics CorporationInventor: John D. Prymak
-
Patent number: 7969711Abstract: A Zener diode—capacitor combination wherein a Zener diode is mounted in the capacitor body and connected in parallel with the capacitor after the capacitor has been voltage tested. A welded strap or jumper wire completing the diode circuit or a connection of separate terminations during soldering may be used to complete the circuit.Type: GrantFiled: February 6, 2008Date of Patent: June 28, 2011Assignee: Kemet Electronics CorporationInventors: John D. Prymak, Eric Jayson Young
-
Publication number: 20110096521Abstract: A capacitive interposer, electronic package having the capacitive interposer and electronic device with the electronic package is described. The interposer has a first planar face and a second planar face. An array of upper connections is on the first planar face and opposing lower connections are on the second planar face with conduction paths between each upper connection of the upper connections and a lower connection of the lower connections. At least one power feed-through capacitor is provided. The capacitor has a plurality of parallel plates with a dielectric there between. At least one first external termination is in electrical contact with a first set of alternate parallel plates and at least one second external termination is in electrical contact with a second set of alternate parallel plates.Type: ApplicationFiled: February 12, 2008Publication date: April 28, 2011Inventors: Michael Randall, Renner Garry, John D. Prymak, Tajuddin Azizuddin
-
Patent number: 7833293Abstract: A Zener diode-capacitor combination wherein a Zener diode is mounted in the capacitor body and connected in parallel with the capacitor after the capacitor has been voltage tested. A welded strap or jumper wire completing the diode circuit or a connection of separate terminations during soldering may be used to complete the circuit.Type: GrantFiled: March 10, 2010Date of Patent: November 16, 2010Assignee: KEMET Electronics CorporationInventors: John D. Prymak, Eric Jayson Young
-
Publication number: 20100162563Abstract: A Zener diode-capacitor combination wherein a Zener diode is mounted in the capacitor body and connected in parallel with the capacitor after the capacitor has been voltage tested. A welded strap or jumper wire completing the diode circuit or a connection of separate terminations during soldering may be used to complete the circuit.Type: ApplicationFiled: March 10, 2010Publication date: July 1, 2010Inventors: John D. Prymak, Eric Jayson Young
-
Patent number: 7745281Abstract: An improved method for forming a capacitor. The method includes the steps of: providing a metal foil; forming a dielectric on the metal foil; applying a non-conductive polymer dam on the dielectric to isolate discrete regions of the dielectric; forming a cathode in at least one discrete region of the discrete regions on the dielectric; and cutting the metal foil at the non-conductive polymer dam to isolate at least one capacitor comprising one cathode, one discrete region of the dielectric and a portion of the metal foil with the discrete region of the dielectric.Type: GrantFiled: February 14, 2008Date of Patent: June 29, 2010Assignees: Kemet Electronics Corporation, Motorola, Inc.Inventors: John D. Prymak, Chris Stolarski, David Jacobs, Chris Wayne, Philip Lessner, John T. Kinard, Alethia Melody, Gregory Dunn, Robert T. Croswell, Remy J. Chelini