Patents by Inventor John D. Sylvestri
John D. Sylvestri has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11940271Abstract: A method of preparing a computer processor die includes determining a warpage shape of the computer processor die at a testing temperature. The method also includes selectively contouring a thickness of the computer processor die at a contouring temperature by physically removing material from a surface of the computer processor die such that the surface will be substantially flat at the testing temperature.Type: GrantFiled: November 17, 2020Date of Patent: March 26, 2024Assignee: International Business Machines CorporationInventors: David J. Lewison, Jay A. Bunt, Frank L. Pompeo, Richard Walter Oldrey, John D. Sylvestri, Phong T. Tran
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Publication number: 20220155049Abstract: A method of preparing a computer processor die includes determining a warpage shape of the computer processor die at a testing temperature. The method also includes selectively contouring a thickness of the computer processor die at a contouring temperature by physically removing material from a surface of the computer processor die such that the surface will be substantially flat at the testing temperature.Type: ApplicationFiled: November 17, 2020Publication date: May 19, 2022Inventors: David J. Lewison, Jay A. Bunt, Frank L. Pompeo, Richard Walter Oldrey, John D. Sylvestri, Phong T. Tran
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Patent number: 7993504Abstract: A method and system for backside unlayering a semiconductor device to expose FEOL semiconductor features of the device for subsequent electrical and/or physical probing. A window is formed within a backside substrate layer of the semiconductor. A collimated ion plasma is generated and directed so as to contact the semiconductor only within the backside window via an opening in a focusing shield. This focused collimated ion plasma contacts the semiconductor, only within the window, while the semiconductor is simultaneously being rotated and tilted by a temperature controlled stage, for uniform removal of semiconductor layering such that the semiconductor features, in a location on the semiconductor corresponding to the backside window, are exposed. Backside unlayering of the invention may be enhanced by CAIBE processing.Type: GrantFiled: February 7, 2008Date of Patent: August 9, 2011Assignee: International Business Machines CorporationInventors: Terence L. Kane, Darrell L. Miles, John D. Sylvestri, Michael P. Tenney
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Patent number: 7961307Abstract: A structure for locating a fault in a semiconductor chip. The chip includes a substrate on a dielectric interconnect. A first electrical response image of the chip, which includes a spot representing the fault, is overlayed on a first reflection image for monochromatic light in an optical path from an optical microscope through a SIL/NAIL and into the chip. The index of refraction of the substrate exceeds that of the dielectric interconnect and is equal to that of the SIL/NAIL. A second electrical response image of the chip is overlayed on a second reflection image for the monochromatic light in an optical path in which an optical stop prevents all subcritical angular components of the monochromatic light from being incident on the SIL/NAIL. If the second electrical response image includes or does not include the spot, then the fault is in the substrate or the dielectric interconnect, respectively.Type: GrantFiled: October 26, 2010Date of Patent: June 14, 2011Assignee: International Business Machines CorporationInventors: Stephen Bradley Ippolito, Darrell L. Miles, Peilin Song, John D. Sylvestri
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Publication number: 20110037973Abstract: A structure for locating a fault in a semiconductor chip. The chip includes a substrate on a dielectric interconnect. A first electrical response image of the chip, which includes a spot representing the fault, is overlayed on a first reflection image for monochromatic light in an optical path from an optical microscope through a SIL/NAIL and into the chip. The index of refraction of the substrate exceeds that of the dielectric interconnect and is equal to that of the SIL/NAIL. A second electrical response image of the chip is overlayed on a second reflection image for the monochromatic light in an optical path in which an optical stop prevents all subcritical angular components of the monochromatic light from being incident on the SIL/NAIL. If the second electrical response image includes or does not include the spot, then the fault is in the substrate or the dielectric interconnect, respectively.Type: ApplicationFiled: October 26, 2010Publication date: February 17, 2011Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Stephen Bradley Ippolito, Darrell L. Miles, Peilin Song, John D. Sylvestri
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Patent number: 7826045Abstract: A method and structure for locating a fault in a semiconductor chip. The chip includes a substrate on a dielectric interconnect. A first electrical response image of the chip, which includes a spot representing the fault, is overlayed on a first reflection image for monochromatic light in an optical path from an optical microscope through a SIL/NAIL and into the chip. The index of refraction of the substrate exceeds that of the dielectric interconnect and is equal to that of the SIL/NAIL. A second electrical response image of the chip is overlayed on a second reflection image for the monochromatic light in an optical path in which an optical stop prevents all subcritical angular components of the monochromatic light from being incident on the SIL/NAIL. If the second electrical response image includes or does not include the spot, then the fault is in the substrate or the dielectric interconnect, respectively.Type: GrantFiled: January 25, 2008Date of Patent: November 2, 2010Assignee: International Business Machines CorporationInventors: Stephen Bradley Ippolito, Darrell L. Miles, Peilin Song, John D. Sylvestri
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Publication number: 20090189630Abstract: A method and structure for locating a fault in a semiconductor chip. The chip includes a substrate on a dielectric interconnect. A first electrical response image of the chip, which includes a spot representing the fault, is overlayed on a first reflection image for monochromatic light in an optical path from an optical microscope through a SIL/NAIL and into the chip. The index of refraction of the substrate exceeds that of the dielectric interconnect and is equal to that of the SIL/NAIL. A second electrical response image of the chip is overlayed on a second reflection image for the monochromatic light in an optical path in which an optical stop prevents all subcritical angular components of the monochromatic light from being incident on the SIL/NAIL. If the second electrical response image includes or does not include the spot, then the fault is in the substrate or the dielectric interconnect, respectively.Type: ApplicationFiled: January 25, 2008Publication date: July 30, 2009Inventors: Stephen Bradley Ippolito, Darrell L. Miles, Peilin Song, John D. Sylvestri
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Publication number: 20080272474Abstract: An apparatus for implementing integrated circuit cooling during testing and image-based analysis thereof includes a lid configured to define a cavity surrounding an integrated circuit die, the die mounted to a module substrate. One or more fluid passages are defined within the lid, wherein the passages facilitate the flow of a cooling liquid through said cavity and over the integrated circuit die, and a transparent window is formed within the lid so as to facilitate viewing of the integrated circuit die.Type: ApplicationFiled: July 17, 2008Publication date: November 6, 2008Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Patrick J. McGinnis, Darrell L. Miles, Richard W. Oldrey, John D. Sylvestri, Manuel J. Villalobos
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Publication number: 20080227247Abstract: The present invention provides a semiconducting device including a gate dielectric atop a semiconducting substrate, the semiconducting substrate containing source and drain regions adjacent the gate dielectric; a gate conductor atop the gate dielectric; a conformal dielectric passivation stack positioned on at least the gate conductor sidewalls, the conformal dielectric passivation stack comprising a plurality of conformal dielectric layers, wherein no electrical path extends entirely through the stack; and a contact to the source and drain regions, wherein the discontinuous seam through the conformal dielectric passivation stack substantially eliminates shorting between the contact and the gate conductor. The present invention also provides a method for forming the above-described semiconducting device.Type: ApplicationFiled: May 29, 2008Publication date: September 18, 2008Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Brett H. Engel, Stephen M. Lucarini, John D. Sylvestri, Yun-Yu Wang
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Patent number: 7397073Abstract: The present invention provides a semiconducting device including a gate dielectric atop a semiconducting substrate, the semiconducting substrate containing source and drain regions adjacent the gate dielectric; a gate conductor atop the gate dielectric; a conformal dielectric passivation stack positioned on at least the gate conductor sidewalls, the conformal dielectric passivation stack comprising a plurality of conformal dielectric layers, wherein no electrical path extends entirely through the stack; and a contact to the source and drain regions, wherein the discontinuous seam through the conformal dielectric passivation stack substantially eliminates shorting between the contact and the gate conductor. The present invention also provides a method for forming the above-described semiconducting device.Type: GrantFiled: November 22, 2004Date of Patent: July 8, 2008Assignee: International Business Machines CorporationInventors: Brett H. Engel, Stephen M. Lucarini, John D. Sylvestri, Yun-Yu Wang
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Publication number: 20080128086Abstract: A method and system for backside unlayering a semiconductor device to expose FEOL semiconductor features of the device for subsequent electrical and/or physical probing. A window is formed within a backside substrate layer of the semiconductor. A collimated ion plasma is generated and directed so as to contact the semiconductor only within the backside window via an opening in a focusing shield. This focused collimated ion plasma contacts the semiconductor, only within the window, while the semiconductor is simultaneously being rotated and tilted by a temperature controlled stage, for uniform removal of semiconductor layering such that the semiconductor features, in a location on the semiconductor corresponding to the backside window, are exposed. Backside unlayering of the invention may be enhanced by CAIBE processing.Type: ApplicationFiled: February 7, 2008Publication date: June 5, 2008Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Terence L. Kane, Darrell L. Miles, John D. Sylvestri, Michael P. Tenney
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Patent number: 7371689Abstract: A method and system for backside unlayering a semiconductor device to expose FEOL semiconductor features of the device for subsequent electrical and/or physical probing. A window is formed within a backside substrate layer of the semiconductor. A collimated ion plasma is generated and directed so as to contact the semiconductor only within the backside window via an opening in a focusing shield. This focused collimated ion plasma contacts the semiconductor, only within the window, while the semiconductor is simultaneously being rotated and tilted by a temperature controlled stage, for uniform removal of semiconductor layering such that the semiconductor features, in a location on the semiconductor corresponding to the backside window, are exposed. Backside unlayering of the invention may be enhanced by CAIBE processing.Type: GrantFiled: October 3, 2005Date of Patent: May 13, 2008Assignee: International Business Machines CorporationInventors: Terence L Kane, Darrell L Miles, John D Sylvestri, Michael P Tenney
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Patent number: 7112983Abstract: An apparatus for facilitating single die backside probing of semiconductor devices includes a chip holder configured for receiving a single integrated circuit die attached thereto, the chip holder maintained in flexible engagement in an X-Y orientation with respect to a lift plate. A lift ring is coupled to the lift plate, the lift ring configured to facilitate adjustment of the lift plate and the chip holder in a Z-direction.Type: GrantFiled: November 10, 2004Date of Patent: September 26, 2006Assignee: International Business Machines CorporationInventors: Patrick J. McGinnis, Darrell L. Miles, Richard W. Oldrey, John D. Sylvestri, Manuel J. Villalobos
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Patent number: 7038474Abstract: A technique is described for performing critical parameter analysis (CPA) of a semiconductor device (DUT) by combining the capabilities of conventional automated test equipment (ATE) with a focused optical beam scanning device such as a laser scanning microscope (LSM). The DUT is provided with a fixture such that it can be simultaneously scanned by the LSM or a similar device and exercised by the ATE. The ATE is used to determine pass/fail boundaries of operation of the DUT. Repeatable pass/fail limits (for timing, levels, etc.) are determined utilizing standard test patterns and methodologies. The ATE vector pattern(s) can then be programmed to “loop” the test under a known passing or failing state. When light energy from the LSM scanning beam sufficiently disturbs the DUT to produce a transition (i.e.Type: GrantFiled: September 24, 2004Date of Patent: May 2, 2006Assignee: International Business Machines CorporationInventors: Patrick J. McGinnis, John D. Sylvestri
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Patent number: 6894522Abstract: A method for implementing backside probing of a semiconductor device includes isolating an identified defect area on a backside of the semiconductor device, and milling the identified defect area to an initial depth. Edges of the identified defect area are masked, wherein unmasked semiconductor material, beginning at the initial depth, is etched for a plurality of timed intervals until one or more active devices are reached. The one or more active devices are electrically probed.Type: GrantFiled: October 6, 2003Date of Patent: May 17, 2005Assignee: International Business Machines CorporationInventors: Barbara A. Averill, Terence Kane, Darrell L. Miles, Richard W. Oldrey, John D. Sylvestri