Patents by Inventor John David Allison

John David Allison has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Interrupts between asynchronously operating CPUs in fault tolerant computer system
    Patent number: 5890003
    Abstract: A computer system in a fault-tolerant configuration employs three identical CPUs executing the same instruction stream, with two identical, self-checking memory modules storing duplicates of the same data. Memory references by the three CPUs are made by three separate busses connected to three separate ports of each of the two memory modules. The three CPUs are loosely synchronized, as by detecting events such as memory references and stalling any CPU ahead of others until all execute the function simultaneously; interrupts can be synchronized by ensuring that all three CPUs implement the interrupt at the same point in their instruction stream. Memory references via the separate CPU-to-memory busses are voted at the three separate ports of each of the memory modules. I/O functions are implemented using two identical I/O busses, each of which is separately coupled to only one of the memory modules. A number of I/O processors are coupled to both I/O busses.
    Type: Grant
    Filed: September 7, 1993
    Date of Patent: March 30, 1999
    Assignee: Tandem Computers Incorporated
    Inventors: Richard W. Cutts, Jr., Kenneth C. Debacker, Robert W. Horst, Nikhil A. Mehta, Douglas E. Jewett, John David Allison, Richard A. Southworth
  • Refresh control for dynamic memory in multiple processor system
    Patent number: 5758113
    Abstract: A computer system in a fault-tolerant configuration employs three identical CPUs executing the same instruction stream, with two identical, self-checking memory modules storing duplicates of the same data. Memory references by the three CPUs are made by three separate busses connected to three separate ports of each of the two memory modules. The three CPUs are loosely synchronized, as by detecting events such as memory references and stalling any CPU ahead of others until all execute the function simultaneously; interrupts can be synchronized by ensuring that all three CPUs implement the interrupt at the same point in their instruction stream. Memory references via the separate CPU-to-memory busses are voted at the three separate ports of each of the memory modules. I/O functions are implemented using two identical I/O busses, each of which is separately coupled to only one of the memory modules. A number of I/O processors are coupled to both I/O busses.
    Type: Grant
    Filed: March 10, 1997
    Date of Patent: May 26, 1998
    Assignee: Tandem Computers Incorporated
    Inventors: Charles E. Peet, Jr., John David Allison, Kenneth C. Debacker, Robert W. Horst