Patents by Inventor John David Baniecki

John David Baniecki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6882516
    Abstract: The present invention comprises the steps of (a) forming a first electrode on a substrate via an adhesion enhancing layer, (b) forming a capacitor insulating film containing a laminated film, in which an amorphous dielectric film and a polycrystalline dielectric film are laminated via a wave-like interface, by forming sequentially and successively the amorphous dielectric film and the polycrystalline dielectric film made of same material on the first electrode, (c) forming a second electrode on the capacitor insulating film, and (d) a step of annealing the capacitor insulating film in an oxygen atmosphere.
    Type: Grant
    Filed: February 13, 2003
    Date of Patent: April 19, 2005
    Assignee: Fujitsu Limited
    Inventors: John David Baniecki, Takeshi Shioga, Kazuaki Kurihara
  • Patent number: 6853051
    Abstract: A thin film capacitor comprising an insulating substrate, a capacitor structure located on the substrate, the capacitor structure having a dielectric layer sandwiched between a lower electrode layer and an upper electrode layer, and conductor members respectively connected to the lower electrode layer and the upper electrode layer, wherein at least the dielectric layer has a side face having a sufficient slope for preventing the short circuit of the upper electrode layer with the lower electrode layer through the conductor member. A method of manufacturing such a thin film capacitor is also disclosed.
    Type: Grant
    Filed: December 24, 2002
    Date of Patent: February 8, 2005
    Assignee: Fujitsu Limited
    Inventors: Takeshi Shioga, John David Baniecki, Kazuaki Kurihara
  • Publication number: 20040239349
    Abstract: A probe card includes probes, a build-up interconnection layer having a multilayer interconnection structure therein and carrying the probes on a top surface in electrical connection with the multilayer interconnection structure, and a capacitor provided on the build-up interconnection layer in electrical connection with one of the probes via the multilayer interconnection structure, wherein the multilayer interconnection structure includes an inner via-contact in the vicinity of the probe and the capacitor is embedded in a resin insulation layer constituting the build-up layer.
    Type: Application
    Filed: July 18, 2003
    Publication date: December 2, 2004
    Applicant: FUJITSU LIMITED
    Inventors: Yasuo Yamagishi, Takeshi Shioga, John David Baniecki, Kazuaki Kurihara
  • Patent number: 6803617
    Abstract: The capacitor comprises an lower electrode 22, a dielectric film 30 formed on the lower electrode 22, a floating electrode 20 formed on the dielectric film 30, a dielectric film 50 formed on the floating electrode 40 and having a film orientation different from that of the dielectric film 30, and an upper electrode 80 formed on the dielectric film 50, whereby various characteristics depending on film orientations of the dielectric films can be simultaneously improved.
    Type: Grant
    Filed: January 13, 2003
    Date of Patent: October 12, 2004
    Assignee: Fujitsu Limited
    Inventors: John David Baniecki, Takeshi Shioga, Kazuaki Kurihara
  • Publication number: 20040178436
    Abstract: An integrated thin film capacitive element comprising a dielectric material of the specified composition that exhibits increased voltage tunability of capacitance and capacitance density and a production process thereof are disclosed. The integrated thin film capacitive element comprises a capacitor structure constituted from a lower electrode, a dielectric layer comprised of the high dielectric constant material represented by the formula: (Ba(1-y)(1-x)Sr(1-y)xYy)Ti1+zO3+&dgr; with the range 0<x<1, 0.007<y<0.02, −1<&dgr;<0.5, and (Ba(1-y)(1-x)+Sr(1-y)x)/Ti1+z<1, and an upper electrode. An electronic device comprising the capacitive element of the present invention is also disclosed.
    Type: Application
    Filed: March 3, 2004
    Publication date: September 16, 2004
    Applicant: FUJITSU LIMITED
    Inventors: John David Baniecki, Takeshi Shioga, Kazuaki Kurihara
  • Publication number: 20040130849
    Abstract: In one aspect of the invention, in a thin layer capacitor element comprising a capacitor having a dielectric layer made of a metal oxide and a protective insulating layer made of a resin material, a barrier layer made of a non-conductive inorganic material is provided between the capacitor and the protective insulating layer. In another aspect of the invention, a thin layer capacitor element is constituted so that a capacitor structure is covered with at least one protective insulating layer composed of a cured resin, the cured resin being formed from at least one resin precursor selected from the group consisting of thermosetting resins, photosetting resins and thermoplastic resins.
    Type: Application
    Filed: November 13, 2003
    Publication date: July 8, 2004
    Inventors: Kazuaki Kurihara, Takeshi Shioga, John David Baniecki, Mamoru Kurashina
  • Patent number: 6717199
    Abstract: A method for tailoring properties of high k thin layer perovskite materials, and devices comprising such insulators are herein presented. The method comprise the steps of, first, substantially completing the manufacture of a device, which device contains the high k insulator in a polycrystalline form. The device, such as a capacitor, or an FET, went through the typically high temperature manufacturing process of a fabrication line. In the next step, the device is in situ ion implanted with such a dose and energy to convert a fraction of the polycrystalline material into an amorphous material state, hereby tailoring the properties of the insulator. The fraction of polycrystalline material converted to amorphous material might be 1. This process can be applied to many electronic devices and some optical devices. The process results in novel perovskite thin layer materials and novel devices fabricated with such materials.
    Type: Grant
    Filed: April 4, 2003
    Date of Patent: April 6, 2004
    Assignee: International Business Machines Corporation
    Inventors: Robert Benjamin Laibowitz, John David Baniecki, Johannes Georg Bednorz, Jean-Pierre A. Locquet
  • Publication number: 20040012085
    Abstract: A semiconductor device comprises a carrier substrate, an integrated circuit chip mounted on the carrier substrate via bumps, and a capacitor provided to stabilize operation of the integrated circuit chip at high frequencies. In the semiconductor device, the capacitor is electrically connected to pads on bottom of the integrated circuit chip, and the capacitor is provided to have a height on the carrier substrate that is smaller than or equal to a height of the bumps on the carrier substrate.
    Type: Application
    Filed: July 16, 2003
    Publication date: January 22, 2004
    Applicant: FUJITSU LIMITED
    Inventors: Takeshi Shioga, John David Baniecki, Kazuaki Kurihara, Yasuo Yamagishi
  • Publication number: 20040000667
    Abstract: The present invention provides a novel capacitor element, laminated thin-film device, and circuit wherein the capacitance dependency on voltage can be appropriately adjusted, and a technology for manufacturing such a capacitor element and laminated thin-film device. In the capacitor element that comprises a pair of electrode layers and a dielectric layer disposed between the electrode layers, a well region where an ion is implanted is disposed in the dielectric layer, and the C-V curve between the electrode layers is shifted or shifted and expanded in at least one direction of the plus direction and minus direction with respect to the voltage axis.
    Type: Application
    Filed: June 11, 2003
    Publication date: January 1, 2004
    Applicant: FUJITSU LIMITED
    Inventors: John David Baniecki, Takeshi Shioga, Kazuaki Kurihara
  • Publication number: 20030209745
    Abstract: A method for tailoring properties of high k thin layer perovskite materials, and devices comprising such insulators are herein presented. The method comprise the steps of, first, substantially completing the manufacture of a device, which device contains the high k insulator in a polycrystalline form. The device, such as a capacitor, or an FET, went through the typically high temperature manufacturing process of a fabrication line. In the next step, the device is in situ ion implanted with such a dose and energy to convert a fraction of the polycrystalline material into an amorphous material state, hereby tailoring the properties of the insulator. The fraction of polycrystalline material converted to amorphous material might be 1. This process can be applied to many electronic devices and some optical devices. The process results in novel perovskite thin layer materials and novel devices fabricated with such materials.
    Type: Application
    Filed: April 4, 2003
    Publication date: November 13, 2003
    Applicant: International Business Machines Corporation
    Inventors: Robert Benjamin Laibowitz, John David Baniecki, Johannes Georg Bednorz, Jean-Pierre A. Locquet
  • Publication number: 20030184952
    Abstract: The present invention comprises the steps of (a) forming a first electrode on a substrate via an adhesion enhancing layer, (b) forming a capacitor insulating film containing a laminated film, in which an amorphous dielectric film and a polycrystalline dielectric film are laminated via a wave-like interface, by forming sequentially and successively the amorphous dielectric film and the polycrystalline dielectric film made of same material on the first electrode, (c) forming a second electrode on the capacitor insulating film, and (d) a step of annealing the capacitor insulating film in an oxygen atmosphere.
    Type: Application
    Filed: February 13, 2003
    Publication date: October 2, 2003
    Applicant: FUJITSU LIMITED
    Inventors: John David Baniecki, Takeshi Shioga, Kazuaki Kurihara
  • Publication number: 20030136998
    Abstract: The capacitor comprises an lower electrode 22, a dielectric film 30 formed on the lower electrode 22, a floating electrode 20 formed on the dielectric film 30, a dielectric film 50 formed on the floating electrode 40 and having a film orientation different from that of the dielectric film 30, and an upper electrode 80 formed on the dielectric film 50, whereby various characteristics depending on film orientations of the dielectric films can be simultaneously improved.
    Type: Application
    Filed: January 13, 2003
    Publication date: July 24, 2003
    Applicant: FUJITSU LIMITED
    Inventors: John David Baniecki, Takeshi Shioga, Kazuaki Kurihara
  • Publication number: 20030136997
    Abstract: A thin film capacitor comprising an insulating substrate, a capacitor structure located on the substrate, the capacitor structure having a dielectric layer sandwiched between a lower electrode layer and an upper electrode layer, and conductor members respectively connected to the lower electrode layer and the upper electrode layer, wherein at least the dielectric layer has a side face having a sufficient slope for preventing the short circuit of the upper electrode layer with the lower electrode layer through the conductor member. A method of manufacturing such a thin film capacitor is also disclosed.
    Type: Application
    Filed: December 24, 2002
    Publication date: July 24, 2003
    Inventors: Takeshi Shioga, John David Baniecki, Kazuaki Kurihara
  • Patent number: 6593181
    Abstract: A method for tailoring properties of high k thin layer perovskite materials, and devices comprising such insulators are herein presented. The method comprise the steps of, first, substantially completing the manufacture of a device, which device contains the high k insulator in a polycrystalline form. The device, such as a capacitor, or an FET, went through the typically high temperature manufacturing process of a fabrication line. In the next step, the device is in situ ion implanted with such a dose and energy to convert a fraction of the polycrystalline material into an amorphous material state, hereby tailoring the properties of the insulator. The fraction of polycrystalline material converted to amorphous material might be 1. This process can be applied to many electronic devices and some optical devices. The process results in novel perovskite thin layer materials and novel devices fabricated with such materials.
    Type: Grant
    Filed: April 20, 2001
    Date of Patent: July 15, 2003
    Assignee: International Business Machines Corporation
    Inventors: Robert Benjamin Laibowitz, John David Baniecki, Johannes Georg Bednorz, Jean-Pierre A. Locquet
  • Publication number: 20020153549
    Abstract: A method for tailoring properties of high k thin layer perovskite materials, and devices comprising such insulators are herein presented. The method comprise the steps of, first, substantially completing the manufacture of a device, which device contains the high k insulator in a polycrystalline form. The device, such as a capacitor, or an FET, went through the typically high temperature manufacturing process of a fabrication line. In the next step, the device is in situ ion implanted with such a dose and energy to convert a fraction of the polycrystalline material into an amorphous material state, hereby tailoring the properties of the insulator. The fraction of polycrystalLine material converted to amorphous material might be 1. This process can be applied to many electronic devices and some optical devices. The process results in novel perovskite thin layer materials and novel devices fabricated with such materials.
    Type: Application
    Filed: April 20, 2001
    Publication date: October 24, 2002
    Inventors: Robert Benjamin Laibowitz, John David Baniecki, Johannes Georg Bednorz, Jean-Pierre A. Locquet