Patents by Inventor John Dinh Hoang

John Dinh Hoang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Wafer level burn-in and electrical test system and method
    Patent number: 7928754
    Abstract: A burn-in and electrical test system (20) includes a temperature controlled zone (22) and a cool zone (24) separated by a transition zone 25. The temperature controlled zone (22) is configured to receive a plurality of wafer cartridges (26) and connect the cartridges (26) to test electronics (28) and power electronics (30), which are mounted in the cool zone (24). Each of the wafer cartridges (26) contains a semiconductor wafer incorporating a plurality of integrated circuits. The test electronics (28) consists of a pattern generator PCB (100) and a signal driver and fault analysis PCB (102) connected together by a parallel bus (104). The pattern generator PCB (100) and the fault analysis PCB (102) are connected to a rigid signal probe PCB (104) in cartridge (26) to provide a straight through signal path.
    Type: Grant
    Filed: October 6, 2009
    Date of Patent: April 19, 2011
    Assignee: Aehr Test Systems
    Inventors: Donald Paul Richmond, II, John Dinh Hoang, Jerzy Lobacz
  • Wafer Level Burn-In and Electrical Test System and Method
    Publication number: 20100176836
    Abstract: A burn-in and electrical test system (20) includes a temperature controlled zone (22) and a cool zone (24) separated by a transition zone 25. The temperature controlled zone (22) is configured to receive a plurality of wafer cartridges (26) and connect the cartridges (26) to test electronics (28) and power electronics (30), which are mounted in the cool zone (24). Each of the wafer cartridges (26) contains a semiconductor wafer incorporating a plurality of integrated circuits. The test electronics (28) consists of a pattern generator PCB (100) and a signal driver and fault analysis PCB (102) connected together by a parallel bus (104). The pattern generator PCB (100) and the fault analysis PCB (102) are connected to a rigid signal probe PCB (104) in cartridge (26) to provide a straight through signal path.
    Type: Application
    Filed: October 6, 2009
    Publication date: July 15, 2010
    Inventors: Donald Paul Richmond, II, John Dinh Hoang, Jerzy Lobacz
  • Wafer level burn-in and electrical test system and method
    Patent number: 7619428
    Abstract: A burn-in and electrical test system (20) includes a temperature controlled zone (22) and a cool zone (24) separated by a transition zone 25. The temperature controlled zone (22) is configured to receive a plurality of wafer cartridges (26) and connect the cartridges (26) to test electronics (28) and power electronics (30), which are mounted in the cool zone (24). Each of the wafer cartridges (26) contains a semiconductor wafer incorporating a plurality of integrated circuits. The test electronics (28) consists of a pattern generator PCB (100) and a signal driver and fault analysis PCB (102) connected together by a parallel bus (104). The pattern generator PCB (100) and the fault analysis PCB (102) are connected to a rigid signal probe PCB (104) in cartridge (26) to provide a straight through signal path.
    Type: Grant
    Filed: November 21, 2003
    Date of Patent: November 17, 2009
    Assignee: Aehr Test Systems
    Inventors: Donald Paul Richmond, II, John Dinh Hoang, Jerzy Lobacz
  • Wafer level burn-in and electrical test system and method
    Publication number: 20040113645
    Abstract: A burn-in and electrical test system (20) includes a temperature controlled zone (22) and a cool zone (24) separated by a transition zone 25. The temperature controlled zone (22) is configured to receive a plurality of wafer cartridges (26) and connect the cartridges (26) to test electronics (28) and power electronics (30), which are mounted in the cool zone (24). Each of the wafer cartridges (26) contains a semiconductor wafer incorporating a plurality of integrated circuits. The test electronics (28) consists of a pattern generator PCB (100) and a signal driver and fault analysis PCB (102) connected together by a parallel bus (104). The pattern generator PCB (100) and the fault analysis PCB (102) are connected to a rigid signal probe PCB (104) in cartridge (26) to provide a straight through signal path.
    Type: Application
    Filed: November 21, 2003
    Publication date: June 17, 2004
    Applicant: Aehr Test Systems
    Inventors: Donald Paul Richmond, John Dinh Hoang, Jerzy Lobacz
  • Wafer level burn-in and electrical test system and method
    Patent number: 6682945
    Abstract: A burn-in and electrical test system (20) includes a temperature controlled zone (22) and a cool zone (24) separated by a transition zone 25. The temperature controlled zone (22) is configured to receive a plurality of wafer cartridges (26) and connect the cartridges (26) to test electronics (28) and power electronics (30), which are mounted in the cool zone (24). Each of the wafer cartridges (26) contains a semiconductor wafer incorporating a plurality of integrated circuits. The test electronics (28) consists of a pattern generator PCB (100) and a signal driver and fault analysis PCB (102) connected together by a parallel bus (104). The pattern generator PCB (100) and the fault analysis PCB (102) are connected to a rigid signal probe PCB (104) in cartridge (26) to provide a straight through signal path.
    Type: Grant
    Filed: May 25, 2001
    Date of Patent: January 27, 2004
    Assignee: AEHR Test Systems
    Inventors: Donald Paul Richmond, II, John Dinh Hoang, Jerzy Lobacz
  • Wafer level burn-in and electrical test system and method
    Patent number: 6562636
    Abstract: A burn-in and electrical test system (20) includes a temperature controlled zone (22) and a cool zone (24) separated by a transition zone 25. The temperature controlled zone (22) is configured to receive a plurality of wafer cartridges (26) and connect the cartridges (26) to test electronics (28) and power electronics (30), which are mounted in the cool zone (24). Each of the wafer cartridges (26) contains a semiconductor wafer incorporating a plurality of integrated circuits. The test electronics (28) consists of a pattern generator PCB (100) and a signal driver and fault analysis PCB (102) connected together by a parallel bus (104). The pattern generator PCB (100) and the fault analysis PCB (102) are connected to a rigid signal probe PCB (104) in cartridge (26) to provide a straight through signal path.
    Type: Grant
    Filed: July 14, 1999
    Date of Patent: May 13, 2003
    Assignee: Aehr Test Systems
    Inventors: Donald Paul Richmond, II, John Dinh Hoang, Jerry Lobacz
  • Wafer level burn-in and electrical test system and method
    Publication number: 20020048826
    Abstract: A burn-in and electrical test system (20) includes a temperature controlled zone (22) and a cool zone (24) separated by a transition zone 25. The temperature controlled zone (22) is configured to receive a plurality of wafer cartridges (26) and connect the cartridges (26) to test electronics (28) and power electronics (30), which are mounted in the cool zone (24). Each of the wafer cartridges (26) contains a semiconductor wafer incorporating a plurality of integrated circuits. The test electronics (28) consists of a pattern generator PCB (100) and a signal driver and fault analysis PCB (102) connected together by a parallel bus (104). The pattern generator PCB (100) and the fault analysis PCB (102) are connected to a rigid signal probe PCB (104) in cartridge (26) to provide a straight through signal path.
    Type: Application
    Filed: May 25, 2001
    Publication date: April 25, 2002
    Inventors: Donald Paul Richmond, John Dinh Hoang, Jerzy Lobacz