Abstract: Certain exemplary embodiments can provide a method comprising, responsive to a determination that a machine-readable two-dimensional code has been identified in a first image, said first image comprising a first plurality of pixels defining said machine-readable two-dimensional code and second plurality of pixels defining a non-code zone, automatically causing a saving or displaying of a second image that comprises said machine-readable two-dimensional code or a representation of said machine-readable two-dimensional code and that excludes said non-code zone.

Abstract: Certain exemplary embodiments can provide a method comprising, responsive to a determination that a machine-readable two-dimensional code has been identified in a first image, said first image comprising a first plurality of pixels defining said machine-readable two-dimensional code and second plurality of pixels defining a non-code zone, automatically causing a saving or displaying of a second image that comprises said machine-readable two-dimensional code or a representation of said machine-readable two-dimensional code and that excludes said non-code zone.

Abstract: A flexible, reconfigurable processing system architecture allows for the implementation of a variety of processing system configurations to be implemented on a single device, which is preferably a PCI bus add-in extension board with an attached daughter card attached and electrically connected thereto through a PCI Mezzanine type connector, and which is plugged into a personal computer PCI expansion slot. The architecture uses the PCI bus, for example, as the local CPU bus for an embedded processor, which not only allows for flexibility in system configuration but also allows PCI devices to be hidden from the host CPU to allow for proper system startup. The architecture further permits an embedded processing CPU to be re-booted when the secondary PCI bus host bus bridge fails to respond without affecting host CPU or other secondary PCI bus peripheral devices.

Abstract: A flexible, reconfigurable processing system architecture allows for the implementation of a variety of processing system configurations to be implemented on a single device, which is preferably a PCI bus add-in extension board with an attached daughter card attached and electrically connected thereto through a PCI Mezzanine type connector, and which is plugged into a personal computer PCI expansion slot. The architecture uses the PCI bus, for example, as the local CPU bus for an embedded processor, which not only allows for flexibility in system configuration but also allows PCI devices to be hidden from the host CPU to allow for proper system startup. The architecture further permits an embedded processing CPU to be re-booted when the secondary PCI bus host bus bridge fails to respond without affecting host CPU or other secondary PCI bus peripheral devices.

Abstract: A flexible, reconfigurable processing system architecture allows for the implementation of a variety of processing system configurations to be implemented on a single device, which is preferably a PCI bus add-in extension board with an attached daughter card attached and electrically connected thereto through a PCI Mezzanine type connector, and which is plugged into a personal computer PCI expansion slot. The architecture uses the PCI bus, for example, as the local CPU bus for an embedded processor, which not only allows for flexibility in system configuration but also allows PCI devices to be hidden from the host CPU to allow for proper system startup. The architecture further permits an embedded processing CPU to be re-booted when the secondary PCI bus host bus bridge fails to respond without affecting host CPU or other secondary PCI bus peripheral devices.