Patents by Inventor John E. Barth, Jr.
John E. Barth, Jr. has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8097525Abstract: A semiconductor structure includes at least one silicon substrate having first and second planar surfaces, and at least one through silicon via filled with a conductive material and extending vertically through the first planar surface of the at least one silicon substrate to the second planar surface thereof. The through silicon via forms a vertical interconnection between a plurality of electronic circuits and an amount of dielectric insulation surrounding the through silicon via is varied based on a defined function of the through silicon via.Type: GrantFiled: August 29, 2008Date of Patent: January 17, 2012Assignee: International Business Machines CorporationInventors: John E. Barth, Jr., Kerry Bernstein
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Patent number: 8080851Abstract: A semiconductor structure is disclosed. The semiconductor structure includes a bulk substrate of a first polarity type, a buried insulator layer disposed on the bulk substrate, an active semiconductor layer disposed on top of the buried insulator layer including a shallow trench isolation region and a diffusion region of the first polarity type, a band region of a second polarity type disposed directly beneath the buried insulator layer and forming a conductive path, a well region of the second polarity type disposed in the bulk substrate and in contact with the band region, a deep trench filled with a conductive material of the first polarity type disposed within the well region, and an electrostatic discharge (ESD) protect diode defined by a junction between a lower portion of the deep trench and the well region.Type: GrantFiled: August 29, 2008Date of Patent: December 20, 2011Assignee: International Business Machines CorporationInventors: John E. Barth, Jr., Kerry Bernstein
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Patent number: 8053303Abstract: A semiconductor structure is disclosed. The semiconductor structure includes an active semiconductor layer, a semiconductor device having a gate disposed on top of the active semiconductor layer, and source and drain regions and a body/channel region disposed within the active semiconductor layer, an insulator layer having a first and second side, the first side being adjacent to the active semiconductor layer, a substrate disposed adjacent to the second side of the insulator layer, a body contact disposed under the body/channel region and in the insulator layer. The body contact electrically connects with and contacts with the body/channel region of the semiconductor device and the substrate, to thereby form an ohmic contact and to eliminate floating body effects.Type: GrantFiled: March 30, 2011Date of Patent: November 8, 2011Assignee: International Business Machines CorporationInventors: John E. Barth, Jr., Kerry Bernstein, Francis R. White
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Publication number: 20110267916Abstract: A direct sense memory array architecture and method of operation includes a plurality of memory cells where a bit-line restore voltage level is optimized to reduce memory cell leakage during a first inactive period, and a bit-line preset voltage level is optimized for signal sensing during a second active period. The architecture includes a sense head having of a pair of cross coupled gated inverters. Each of the gated inverters is responsive to a first and second gate control signal which can independently gate a power supply to the inverter circuit within each gated inverter. During the second active period, a first gated inverter senses the data state on the first bit-line, and a second gated inverter performs a preset and write-back function on the first bit-line.Type: ApplicationFiled: April 30, 2010Publication date: November 3, 2011Applicant: International Business Machines CorporationInventor: John E. Barth, JR.
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Patent number: 8024513Abstract: A method for implementing dynamic refresh protocols for DRAM based cache includes partitioning a DRAM cache into a refreshable portion and a non-refreshable portion, and assigning incoming individual cache lines to one of the refreshable portion and the non-refreshable portion of the cache based on a usage history of the cache lines. Cache lines corresponding to data having a usage history below a defined frequency are assigned to the refreshable portion of the cache, and cache lines corresponding to data having a usage history at or above the defined frequency are assigned to the non-refreshable portion of the cache.Type: GrantFiled: December 4, 2007Date of Patent: September 20, 2011Assignee: International Business Machines CorporationInventors: John E. Barth, Jr., Philip G. Emma, Erik L. Hedberg, Hillery C. Hunter, Peter A. Sandon, Vijayalakshmi Srinivasan, Arnold S. Tran
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Patent number: 8014218Abstract: According to an embodiment of the invention, a sense amplifier for, e.g., an array of DRAM data storage cells includes one or more amplifier stages connected together in series. The amplifier stages together form the sense amplifier for the DRAM array. Each amplifier stage includes an isolation capacitor to reduce to a relatively small value any mismatch between the threshold voltages of the transistors within each amplifier stage. A bitline from the DRAM array of memory cells connects to the first amplifier stage. An output from the last amplifier stage connects to a write back switch, the output of which connects to the bitline at the input of the first amplifier stage.Type: GrantFiled: December 24, 2008Date of Patent: September 6, 2011Assignee: International Business Machines CorporationInventor: John E. Barth, Jr.
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Patent number: 7989893Abstract: A semiconductor structure is disclosed. The semiconductor structure includes an active semiconductor layer, a semiconductor device having a gate disposed on top of the active semiconductor layer, and source and drain regions and a body/channel region disposed within the active semiconductor layer, an insulator layer having a first and second side, the first side being adjacent to the active semiconductor layer, a substrate disposed adjacent to the second side of the insulator layer, a body contact disposed under the body/channel region and in the insulator layer. The body contact electrically connects with and contacts with the body/channel region of the semiconductor device and the substrate, to thereby form an ohmic contact and to eliminate floating body effects.Type: GrantFiled: August 28, 2008Date of Patent: August 2, 2011Assignee: International Business Machines CorporationInventors: John E. Barth, Jr., Kerry Bernstein, Francis R. White
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Publication number: 20110180862Abstract: Embodiments of the invention provide an integrated circuit for an embedded dynamic random access memory (eDRAM), a semiconductor-on-insulator (SOI) wafer in which such an integrated circuit may be formed, and a method of forming an eDRAM in such an SOI wafer.Type: ApplicationFiled: January 25, 2010Publication date: July 28, 2011Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Brent A. Anderson, John E. Barth, JR., Herbert L. Ho, Edward J. Nowak, Wayne Trickle
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Publication number: 20110177660Abstract: A semiconductor structure is disclosed. The semiconductor structure includes an active semiconductor layer, a semiconductor device having a gate disposed on top of the active semiconductor layer, and source and drain regions and a body/channel region disposed within the active semiconductor layer, an insulator layer having a first and second side, the first side being adjacent to the active semiconductor layer, a substrate disposed adjacent to the second side of the insulator layer, a deep trench capacitor disposed under the body/channel region of the semiconductor device. The deep trench capacitor electrically connects with and contacts the body/channel region of the semiconductor device, and is located adjacent to the gate of the semiconductor device. The semiconductor structure increases a critical charge Qcrit, thereby reducing a soft error rate (SER) of the semiconductor device.Type: ApplicationFiled: March 30, 2011Publication date: July 21, 2011Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: John E. Barth, JR., Kerry Bernstein, Ethan H. Cannon, Francis R. White
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Publication number: 20110177659Abstract: A semiconductor structure is disclosed. The semiconductor structure includes an active semiconductor layer, a semiconductor device having a gate disposed on top of the active semiconductor layer, and source and drain regions and a body/channel region disposed within the active semiconductor layer, an insulator layer having a first and second side, the first side being adjacent to the active semiconductor layer, a substrate disposed adjacent to the second side of the insulator layer, a body contact disposed under the body/channel region and in the insulator layer. The body contact electrically connects with and contacts with the body/channel region of the semiconductor device and the substrate, to thereby form an ohmic contact and to eliminate floating body effects.Type: ApplicationFiled: March 30, 2011Publication date: July 21, 2011Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: John E. Barth, JR., Kerry Bernstein, Francis R. White
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Publication number: 20110051532Abstract: An approach that provides reference level generation with offset compensation for a sense amplifier is described. In one embodiment, an arbitrary reference level is generated to provide an offset that compensates for device mismatch and voltage threshold of a sense amplifier.Type: ApplicationFiled: August 31, 2009Publication date: March 3, 2011Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: John E. Barth, JR., Erik A. Nelson
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Patent number: 7898078Abstract: Two sets of conductor fins are formed on a topmost surface of stacked semiconductor chips. The two sets of conductor fins are electrically isolated from each other, and function as radiators that dissipate heat from the stacked semiconductor chips. Conductive wiring structures are formed on each set of conductor fins to supply electrical power and electrical grounding to the stacked semiconductor chips. The bottommost surface of the stacked semiconductor chips may be bonded to a packaging substrate. Since the semiconductor fins above provide electrical power supply and electrical grounding, a higher fraction of electrical connections between the bottommost surface of the stacked semiconductor chips and the packaging substrate may be employed for input and output signal transmission without adverse impact on heat dissipation of the stacked semiconductor chips. The conductive fins function as power connectors.Type: GrantFiled: September 29, 2009Date of Patent: March 1, 2011Assignee: International Business Machines CorporationInventors: Kerry Bernstein, John E. Barth, Jr.
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Patent number: 7791977Abstract: A design structure embodied in a machine readable medium used in a design process includes a tri-state power gating apparatus for reducing leakage current in a memory array. The apparatus includes a first distributed header device coupled to the memory array, the first distributed header device is configured for limiting leakage current through the memory array; and a header driver operatively coupled to the first distributed header device for enabling tri-state operation of the first distributed header device, wherein tri-state operation includes sleep mode, wake mode, and retention mode.Type: GrantFiled: May 7, 2008Date of Patent: September 7, 2010Assignee: International Business Machines CorporationInventors: John E. Barth, Jr., Harold Pilo, Vinod Ramadurai
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Patent number: 7791123Abstract: A deep trench containing a doped semiconductor fill portion having a first conductivity type doping and surrounded by a buried plate layer having a second conductivity type doping at a lower portion is formed in a semiconductor layer having a doping of the first conductivity type. A doped well of the second conductivity type abutting the buried plate layer is formed. The doped semiconductor fill portion functions as a temporary reservoir for electrical charges of the first conductivity type that are generated by a radiation particle, and the buried plate layer functions as a temporary reservoir for electrical charges of the second conductivity type. The buried plate layer and the doped semiconductor fill portion forms a capacitor, and provides protection from soft errors to devices formed in the semiconductor layer or the doped well.Type: GrantFiled: March 10, 2008Date of Patent: September 7, 2010Assignee: International Business Machines CorporationInventors: Ethan H. Cannon, John E. Barth, Jr., Kerry Bernstein
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Publication number: 20100157698Abstract: According to an embodiment of the invention, a sense amplifier for, e.g., an array of DRAM data storage cells includes one or more amplifier stages connected together in series. The amplifier stages together form the sense amplifier for the DRAM array. Each amplifier stage includes an isolation capacitor to reduce to a relatively small value any mismatch between the threshold voltages of the transistors within each amplifier stage. A bitline from the DRAM array of memory cells connects to the first amplifier stage. An output from the last amplifier stage connects to a write back switch, the output of which connects to the bitline at the input of the first amplifier stage.Type: ApplicationFiled: December 24, 2008Publication date: June 24, 2010Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventor: John E. Barth, JR.
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Patent number: 7724565Abstract: A design structure embodied in a machine readable medium used in a design process for small signal sensing during a read operation of a static random access memory (SRAM) cell includes coupling a pair of complementary sense amplifier data lines to a corresponding pair of complementary bit lines associated with the SRAM cell, and setting a sense amplifier so as to amplify a signal developed on the sense amplifier data lines, wherein the bit line pair remains coupled to the sense amplifier data lines at the time the sense amplifier is set.Type: GrantFiled: September 6, 2007Date of Patent: May 25, 2010Assignee: International Business Machines CorporationInventors: John E. Barth, Jr., Geordie M. Braceras, Harold Pilo
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Patent number: 7692990Abstract: A circuit for accessing a memory cell includes a local bitline and a local sense amplifier having a plurality of transistors. The local bitline may be connect the memory cell and the sense amplifier. A first global bitline may be connected to a first one of the plurality of transistors. A second global bitline may be connected to a second one of the plurality of transistors. A secondary sense amplifier may be connected to the first and second global bitlines. A design structure embodied in a machine readable medium used in a design process, includes such a circuit for accessing a memory cell.Type: GrantFiled: August 31, 2007Date of Patent: April 6, 2010Assignee: International Business Machines CorporationInventor: John E. Barth, Jr.
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Publication number: 20100052108Abstract: A semiconductor structure includes at least one silicon substrate having first and second planar surfaces, and at least one through silicon via filled with a conductive material and extending vertically through the first planar surface of the at least one silicon substrate to the second planar surface thereof. The through silicon via forms a vertical interconnection between a plurality of electronic circuits and an amount of dielectric insulation surrounding the through silicon via is varied based on a defined function of the through silicon via.Type: ApplicationFiled: August 29, 2008Publication date: March 4, 2010Applicant: International Business Machines CorporationInventors: John E. Barth, JR., Kerry Bernstein
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Publication number: 20100052053Abstract: A semiconductor structure is disclosed. The semiconductor structure includes an active semiconductor layer, a semiconductor device having a gate disposed on top of the active semiconductor layer, and source and drain regions and a body/channel region disposed within the active semiconductor layer, an insulator layer having a first and second side, the first side being adjacent to the active semiconductor layer, a substrate disposed adjacent to the second side of the insulator layer, a body contact disposed under the body/channel region and in the insulator layer. The body contact electrically connects with and contacts with the body/channel region of the semiconductor device and the substrate, to thereby form an ohmic contact and to eliminate floating body effects.Type: ApplicationFiled: August 28, 2008Publication date: March 4, 2010Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: John E. Barth, JR., Kerry Bernstein, Francis R. White
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Publication number: 20100052100Abstract: A semiconductor structure is disclosed. The semiconductor structure includes a bulk substrate of a first polarity type, a buried insulator layer disposed on the bulk substrate, an active semiconductor layer disposed on top of the buried insulator layer including a shallow trench isolation region and a diffusion region of the first polarity type, a band region of a second polarity type disposed directly beneath the buried insulator layer and forming a conductive path, a well region of the second polarity type disposed in the bulk substrate and in contact with the band region, a deep trench filled with a conductive material of the first polarity type disposed within the well region, and an electrostatic discharge (ESD) protect diode defined by a junction between a lower portion of the deep trench and the well region.Type: ApplicationFiled: August 29, 2008Publication date: March 4, 2010Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: John E. Barth, JR., Kerry Bernstein