Abstract: Circuits and methods for performing multilevel power amplification using multiple different supply voltages or states are disclosed. In some embodiments, power amplifiers are provided that switch between three or more supply voltages or states.

Abstract: A radio frequency (RF) power amplifier system or transmitter includes one or more power amplifiers and a controller that is configured to adjust amplitudes and phases of RF input signals of the one or more power amplifiers and supply voltages applied to the one or more power amplifiers. In embodiments where multiple power amplifiers are used, a combiner may be provided to combine outputs of the power amplifiers. In at least one implementation, amplitude adjustment of the RF input signals of the one or more power amplifiers may be used to provide transmit power control and/or power backoff.

Abstract: A radio frequency (RF) transmitter includes one or more power amplifiers and a controller that is configured to adjust amplitudes and phases of RF input signals of the one or more power amplifiers and supply voltages applied to the one or more power amplifiers. In embodiments where multiple power amplifiers are used, a combiner may be provided to combine outputs of the power amplifiers. In at least one implementation, amplitude adjustment of the RF input signals of the one or more power amplifiers may be used to provide transmit power control and/or power backoff for the RF transmitter.

Abstract: A method and apparatus for compressing parameter values for pixels within a frame is accomplished by first grouping pixels in the display frame into a plurality of pixel blocks, where each pixel block includes a plurality of pixels. For at least one of the pixel blocks, the parameter values for the pixel block are translated into a column-wise differential slope representation that represents the parameter values as a plurality of reference points, a plurality of slopes, and a plurality of slope differentials. The column-wise differential slope representation is then transformed into a planar differential slope representation that reduces the representation of the plurality of reference points and the plurality of slopes to a single reference pixel value, two reference slopes, and a plurality of slope differentials.

Abstract: Access to memory is facilitated by a cache memory access system that includes individual buffers for storing and processing data access commands asynchronously, while also assuring data coherency and avoiding deadlock. Data access commands are placed in discrete buffers, in dependence upon their type: read and write to and from a client process, fill from memory, and flush to memory. To maintain data coherency, the read and write commands are processed substantially sequentially. To optimize memory access, fills are processed as soon as they are submitted, and flushes may be given lower priority than fills. To avoid deadlock, fills are generated so as to be independent of all other commands. The use of discrete buffers for cache memory access is particularly well suited to pipeline processes.

Abstract: A method and apparatus for arbitrating access requests to a memory is accomplished which allows for the serialization of the memory access requests, when a memory access collision is detected. A memory access collision is detected when contemporaneous accesses to an identical memory block of the memory occur. Processing begins when a plurality of operations are received via a plurality of parallel pipelines, wherein at least some of the plurality of operations require memory access. The plurality of parallel pipelines are then monitored for memory access collisions. At least some of the plurality of pipelines are then serialized when a memory access collision is detected to ensure proper processing order of the plurality of operations involved in the memory access collision.

Abstract: A data processing system records information on magnetic disks in a format in which sector headers, which include embedded servo information, are radially aligned and recorded at a single frequency and data are recorded at various band-related frequencies. The system records sector headers at a frequency which is optimal for the recording of address information in the shortest sector and records the data at frequencies which are optimal for the recording of information in the disk space allocated to the data portion of the various lengths of sectors. The system synchronizes to the headers, using conventional embedded servo synchronization methods, and produces header timing signals. It can then use the same header timing signals to locate and interpret the headers on different tracks, since the header frequency and the location of the headers are the same in every track. The system may record the data portions of the sectors at frequencies which are related to the header frequency by ratios of small integers.

Abstract: A bus interface between a data bus and data-storage devices provides error protection for multi-byte data packets received from the bus and intended for storage on an associated storage device by checking a packet for errors using check sum symbols and parity bits in the packet. The bus interface then (i) encodes a predetermined number of data symbols to generate error detection symbols, (ii) again checks the data symbols for errors using the parity bits, and (iii) stores the data and associated error detection symbols in one of the series of linked buffers. Each buffer holds enough to fill one storage unit, or sector. A storage interface later retrieves the buffered data and error detection symbols, combines them with the address of a designated storage sector, and encodes the symbols to generate error correction symbols. It then stores the encoded data, and error detection and correction symbols in the designated sector.