Abstract: A family of interconnect structures, switches that exploit the interconnect structures to attain scalability, low latency, and single-chip implementations. The disclosed interconnect structures and switches support a wide variety of applications including supercomputer interconnects, LAN switches, IP and ATM switches, telephony central office switching, video on demand servers, interconnects for mainframe database servers, high-speed workstation interconnects, and many others that are known to those having ordinary skill in the art.

Abstract: An interconnect structure and method of communicating messages on the interconnect structure assists high priority messages to travel through the interconnect structure at a faster rate than normal or low priority messages. An interconnect structure includes a plurality of nodes with a plurality of interconnect lines selectively coupling the nodes in a hierarchical multiple-level structure. Data moves from an uppermost source level to a lowermost destination level. Nodes in the structure are arranged in columns and levels. Data wormholes through the structure and, in a given time-step, data always moves from one column to an adjacent column and while remaining on the same level or moving down to a lower level. When data moves down a level, an additional bit of the target output is fixed so data exiting from the bottom of the structure arrives at the proper target output port.

Abstract: A scalable low-latency switch extends the functionality of a multiple level minimum logic interconnect structure for usage in computers of all types, networks and communication systems. The multiple level minimum logic interconnect structure employs a data flow technique based on timing and positioning of messages moving through the structure. The scalable low-latency switch is distributed throughout multiple nodes in the structure so that a supervisory controller providing a global control function and complex logic structures are avoided while the interconnect structure operates as a “deflection” or “hot potato” system in which processing and storage overhead at each node is reduced. The interconnect structure using the scalable low-latency switch employs a method of achieving wormhole routing through an integrated circuit chip by a novel procedure for inserting messages into the chip.

Abstract: In general a non-reloadable syringe has been provided wherein the plunger unit thereof is permitted to be withdrawn for purposes of loading the syringe and permitted to be urged forwardly to discharge the contents of the syringe. However, means are provided whereby subsequent retraction of the plunger assembly is inhibited to prevent further loading and use of the syringe.