Abstract: A fault-tolerant digital data processing system comprises at least a first input/output controller communicating with at least one peripheral device over a peripheral device bus. The peripheral bus includes first and second input/output buses, each having means for carrying data, address, control, and timing signals. The input/output controller includes an element for applying duplicate information signals synchronously and simultaneously to the first and second input/output buses for transfer to the peripheral device. The input/output controller further includes a bus interface element for receiving, in the absence of fault, duplicative information signals synchronously and simultaneously from the first and second input/output buses.

Abstract: A multi-stage modem status register, which has at least one stage which is ordinarily unused, is employed to receive operating condition signals from an associated modem. In addition bistable circuitry, which exists as part of the control circuitry of a transceiver, is used: (1) to provide a first binary signal when a data processor (with which the present system is used), generates a "resynchronization request" signal; and (2) to provide a second binary signal in response to resynchronization being achieved. The bistable circuitry is connected to the above described ordinarily unused stage to enable one or the other of the binary signals to be present. The multi-stage modem status register is regularly interrogated and the results are sent to both a memory and a comparison device. Output signals from the memory are transmitted to said comparison device, at the time that the results of a subsequent interrogation are transmitted to the comparison device.