Abstract: Method and apparatus for performing voltage sampling. The present invention addresses the problems encountered when a voltage is applied to a voltage sampling circuit (76). An additional capacitor (88) is used to store an amount of charge similar to the amount of charge needed by a primary capacitor (89) which provides an output signal to a voltage receiving circuit (74), such as a portion of a sigma-delta analog to digital converter. The additional capacitor (88) is charged while a primary capacitor (89) is discharged in a first clock phase. Then the additional capacitor (88) and the primary capacitor (89) are both coupled to the voltage to be sampled during a second clock phase.

Abstract: An input stage (200) for use in a Sigma-Delta analog-to-digital converter (300) that utilizes a frequency independent impedance (202) in parallel with a frequency dependent impedance (210, 212). An analog input signal (Vin) is concurrently passed through both impedances to a terminal of an operational amplifier (208). A feedback reference (REF) from the A/D converter (316) is also coupled to the terminal of the op amp (208) via a second frequency independent impedance (204). The frequency dependent impedance (210, 212) enables amplification of the input signal at higher frequencies to boost signal-to-noise ratio at such frequencies. Thus, the frequency dependent impedance significantly improves signal-to-noise ratio in the Sigma-Delta converter, thereby avoiding any pre-filtering of the Sigma-Delta inputs.