Abstract: A signal switch with merged buffer architecture has multiple input ports connected to a circuit switch matrix which partially sorts the input signals based on output port destination. The circuit switch matrix is connected to multiple merged buffers, each in turn connected to a corresponding output port and feedback. Input signals entering the circuit switch matrix are normally sent to the buffer attached to the destination output port of the input signal, but, if more than one input signal is contending for an output port, all but the first contending input signal are misrouted to merged buffers that are not busy. The location in memory of all of the correctly routed and misrouted input signals in the switch is tracked by a control, which also routes input signals to their output port destinations from the merged buffers, and reroutes misrouted input signals to the correct buffers.

Abstract: A write controller for a signal switch with a linearly searchable memory eliminates the need to maintain an ordered list of free addresses. The write controller utilizes a hardware encoded bit map and search logic to search linearly for memory locations that do not contain valid data and can therefore be written to. The search stops at the first memory location where the bit map tag indicates that the memory location is available, and then the write control logic unit associated with that memory location sends a kill signal that tells downstream write control logic units associated with other memory locations to deactivate. The write controller writes the data into the selected memory location and flips the status bit of that location to indicate that the memory location is no longer available for writing. The write controller then releases the restraining kill signal, allowing the next available memory location in line to receive data during the next clock cycle.

Abstract: A switching matrix routes each received input to a unique output port. Each input specifies an output port as a destination. For each output port, a set of inputs contending for the output port is determined. A control for correctly routing selects an input from each set of contending inputs and routes it to the correct output port of the switching matrix. If no input specifies an output port as a destination, that output port is designated as an available output port. A control for misrouting determines the set of available output ports and the set of inputs that have not been correctly routed by the control for correctly routing. The control for misrouting then misroutes each remaining input to one of the available output ports of the switching matrix. The switching matrix may provide status signals for use by the switch in tracking the location of the correctly routed and misrouted inputs.