Patents by Inventor John Eichenseer
John Eichenseer has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8051397Abstract: Method and system for conducting design explorations of an integrated circuit are disclosed. In one embodiment, the method includes obtaining a design description of the integrated circuit that includes a virtual design block, creating a representative netlist for representing the virtual design block, where the representative netlist includes one or more soft design models, and each soft design model comprises one or more template cells for modeling a portion of the integrated circuit. The method further includes defining physical attributes for the one or more soft design models in accordance with area requirements of the virtual design block, where the one or more soft design models are described with flexible shape and pin locations, performing design explorations of the integrated circuit using the one or more soft design models and their corresponding template cells, and generating a representative implementation of the integrated circuit using results of the design explorations.Type: GrantFiled: October 12, 2009Date of Patent: November 1, 2011Assignee: Cadence Design Systems, Inc.Inventors: Thaddeus Clay McCracken, Jong-Chang Lee, Ping-Chih Wu, Cecile Nghiem, Kit Lam Cheong, Patrick John Eichenseer
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Patent number: 7793254Abstract: Aspects for designing a timing closure of an integrated circuit include instantiating a minimum repeater between at least one block and a corresponding blockage if an interconnect crosses the corresponding blockage and according to a drive of the blockage. The aspects further include instantiating one or more smallest repeaters between at least one pair of connected blocks depending upon a drive of a corresponding interconnect, the instantiation of the smallest repeater being based on pre-determined criteria.Type: GrantFiled: July 18, 2007Date of Patent: September 7, 2010Assignee: Cadence Design Systems, Inc.Inventors: Patrick John Eichenseer, Ricky Lewelling, Ziad Sadi
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Publication number: 20100122228Abstract: Method and system for conducting design explorations of an integrated circuit are disclosed. In one embodiment, the method includes obtaining a design description of the integrated circuit that includes a virtual design block, creating a representative netlist for representing the virtual design block, where the representative netlist includes one or more soft design models, and each soft design model comprises one or more template cells for modeling a portion of the integrated circuit. The method further includes defining physical attributes for the one or more soft design models in accordance with area requirements of the virtual design block, where the one or more soft design models are described with flexible shape and pin locations, performing design explorations of the integrated circuit using the one or more soft design models and their corresponding template cells, and generating a representative implementation of the integrated circuit using results of the design explorations.Type: ApplicationFiled: October 12, 2009Publication date: May 13, 2010Applicant: CADENCE DESIGN SYSTEMS, INC.Inventors: Thaddeus Clay MCCRACKEN, Jong-Chang LEE, Ping-Chih WU, Cecile NGHIEM, Kit Lam CHEONG, Patrick John EICHENSEER
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Patent number: 7603643Abstract: Method and system for conducting design explorations of an integrated circuit are disclosed. In one embodiment, the method includes obtaining a design description of the integrated circuit that includes a virtual design block, creating a representative netlist for representing the virtual design block, where the representative netlist includes one or more soft design models, and each soft design model comprises one or more template cells for modeling a portion of the integrated circuit. The method further includes defining physical attributes for the one or more soft design models in accordance with area requirements of the virtual design block, where the one or more soft design models are described with flexible shape and pin locations, performing design explorations of the integrated circuit using the one or more soft design models and their corresponding template cells, and generating a representative implementation of the integrated circuit using results of the design explorations.Type: GrantFiled: January 30, 2007Date of Patent: October 13, 2009Assignee: Cadence Design Systems, Inc.Inventors: Thaddeus Clay McCracken, Jong-Chang Lee, Ping-Chih Wu, Cecile Nghiem, Kit Lam Cheong, Patrick John Eichenseer
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Publication number: 20080184184Abstract: Method and system for conducting design explorations of an integrated circuit are disclosed. In one embodiment, the method includes obtaining a design description of the integrated circuit that includes a virtual design block, creating a representative netlist for representing the virtual design block, where the representative netlist includes one or more soft design models, and each soft design model comprises one or more template cells for modeling a portion of the integrated circuit. The method further includes defining physical attributes for the one or more soft design models in accordance with area requirements of the virtual design block, where the one or more soft design models are described with flexible shape and pin locations, performing design explorations of the integrated circuit using the one or more soft design models and their corresponding template cells, and generating a representative implementation of the integrated circuit using results of the design explorations.Type: ApplicationFiled: January 30, 2007Publication date: July 31, 2008Applicant: Cadence Design Systems, Inc.Inventors: Thaddeus Clay McCracken, Jong-Chang Lee, Ping-Chih Wu, Cecile Nghiem, Kit Lam Cheong, Patrick John Eichenseer
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Patent number: 7257798Abstract: Aspects for designing a timing closure of an integrated circuit include instantiating a minimum repeater between at least one block and a corresponding blockage if an interconnect crosses the corresponding blockage and according to a drive of the blockage. The aspects further include instantiating one or more smallest repeaters between at least one pair of connected blocks depending upon a drive of a corresponding interconnect, the instantiation of the smallest repeater being based on pre-determined criteria.Type: GrantFiled: June 21, 2005Date of Patent: August 14, 2007Assignee: Cadence Design Systems, Inc.Inventors: Patrick John Eichenseer, Ricky Lewelling, Ziad Sadi
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Patent number: 6578183Abstract: When generating a layout for an integrated; circuit (IC) based on a netlist design, a trial layout which need only satisfy the various spatial, power and other constraints, but need not satisfy the layout's timing constraints, is quickly produced. The trial layout acts as a basis for estimating sizes and positions of substrate areas needed to accommodate various modules of the IC and for estimating delays through various signal paths having timing constraints. After producing the trial layout, the IC design is divided into several partitions with modules being grouped into partitions in accordance with their proximity to one another in the trial layout. A floor plan is created which imposes spatial constraints on each partition based on the estimated size and position within the trial layout of the modules forming the partition. A timing budget is also created which allocates portions of each timing constraint to the partitions based on the time delay estimates derived from the trial layout.Type: GrantFiled: October 22, 2001Date of Patent: June 10, 2003Assignee: Silicon Perspective CorporationInventors: Kit-Lam Cheong, Wei-Jin Dai, Hsi-Chuan Chen, Patrick John Eichenseer
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Publication number: 20030079192Abstract: When generating a layout for an integrated circuit (IC) based on a netlist design, a trial layout which need only satisfy the various spatial, power and other constraints, but need not satisfy the layout's timing constraints, is quickly produced. The trial layout acts as a basis for estimating sizes and positions of substrate areas needed to accommodate various modules of the IC and for estimating delays through various signal paths having timing constraints. After producing the trial layout, the IC design is divided into several partitions with modules being grouped into partitions in accordance with their proximity to one another in the trial layout. A floor plan is created which imposes spatial constraints on each partition based on the estimated size and position within the trial layout of the modules forming the partition. A timing budget is also created which allocates portions of each timing constraint to the partitions based on the time delay estimates derived from the trial layout.Type: ApplicationFiled: October 22, 2001Publication date: April 24, 2003Inventors: Kit-Lam Cheong, Wei-Jin Dai, Hsi-Chuan Chen, Patrick John Eichenseer
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Patent number: 6005181Abstract: A control instrument for a system for generating acoustic output which includes a processor for receiving user input signals and control the acoustic output in response to the user input signals. The control instrument includes an instrument body, and at least one sensor element carried by the instrument body. The sensor element generates user input signals upon tactile actuation of the sensor element by a user. The user input signals indicate the location of contact and amount of force applied to the sensor element by the user. A music synthesis system and a sound processing system each including the control instrument are also provided.Type: GrantFiled: April 7, 1998Date of Patent: December 21, 1999Assignee: Interval Research CorporationInventors: Robert L. Adams, Michael Brook, John Eichenseer, Mark Goldstein, Geoff Smith
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Patent number: 5952599Abstract: An improved music generation system that facilitates artistic expression by non-musician and musician performers in both individual and group performance contexts. Mappings are provided between 1) gestures of a performer as indicated by manipulation of a user input device, 2) displayed motion of a graphic object, and 3) global features of a musical segment. The displayed motions and global features are selected so as to reinforce the appearance of causation between the performer's gestures and the produced musical effects and thereby assist the performer in refining his or her musical expression. The displayed motion is isomorphically coherent with the musical segment in order to achieve the appearance of causation. The global features are segment characteristics perceivable to human listeners. Control at the global feature level in combination with isomorphic visual feedback provides advantages to both non-musicians and musicians in producing artistic effect.Type: GrantFiled: November 24, 1997Date of Patent: September 14, 1999Assignee: Interval Research CorporationInventors: Thomas Dolby, Tom Dougherty, John Eichenseer, William Martens, Michael Mills, Joy S. Mountford