Patents by Inventor John Eric Gross

John Eric Gross has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7173475
    Abstract: A signal transmission amplifier circuit has a transmission gate with an input coupled to an input signal. A cross coupled latch is coupled to an output of the transmission gate and has a signal output. A reference generating circuit is coupled to the cross coupled latch.
    Type: Grant
    Filed: March 10, 2004
    Date of Patent: February 6, 2007
    Assignee: Cypress Semiconductor Corp.
    Inventors: Gary Peter Moscaluk, John Eric Gross
  • Patent number: 7158429
    Abstract: A system for read path acceleration has a first strobe reset circuit coupled to a first local amplifier. A second strobe reset circuit is coupled to a second local amplifier. A main amplifier is coupled to an output of the first local amplifier and an output of the second local amplifier.
    Type: Grant
    Filed: March 16, 2004
    Date of Patent: January 2, 2007
    Assignee: Cypress Semiconductor Corp.
    Inventors: Gary Peter Moscaluk, John Eric Gross
  • Patent number: 6707741
    Abstract: A method for reading a memory cell comprising the steps of (A) raising a voltage level of a bitline of the memory cell above a predetermined level, (B) detecting a current flow generated on the bitline in response to the raised voltage level, and (C) coupling one or more sense nodes coupled to the bitline to a ground potential when the current flow is above a predetermined magnitude.
    Type: Grant
    Filed: November 27, 2002
    Date of Patent: March 16, 2004
    Assignee: Cypress Semiconductor Corp.
    Inventors: Thomas M. Mnich, John Eric Gross
  • Patent number: 6501696
    Abstract: A method for reading a memory cell comprising the steps of (A) raising a voltage level of a bitline of the memory cell above a predetermined level, (B) detecting a current flow generated on the bitline in response to the raised voltage level, and (C) coupling one or more sense nodes coupled to the bitline to a ground potential when the current flow is above a predetermined magnitude.
    Type: Grant
    Filed: May 15, 2001
    Date of Patent: December 31, 2002
    Assignee: Cypress Seminconductor Corp.
    Inventors: Thomas M. Mnich, John Eric Gross