Patents by Inventor John Eric Kunz, JR.
John Eric Kunz, JR. has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10026712Abstract: An electrostatic discharge (ESD) protection circuit includes a substrate having a semiconductor surface that the ESD protection circuit formed thereon. A first ESD cell is stacked in series with at least a second ESD cell. An active shunt transistor is electrically in parallel with the first ESD cell or second ESD cell, where the active shunt includes a control node. A trigger circuit has a trigger input and a trigger output, wherein the trigger output is coupled to the control node.Type: GrantFiled: December 2, 2014Date of Patent: July 17, 2018Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: John Eric Kunz, Jr., Farzan Farbiz, Aravind C. Appaswamy, Akram A. Salman
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Patent number: 9692229Abstract: An integrated circuit may include an over-capability detection circuit coupled to an I/O pad which provides a shut-off signal to a latch controlling an ESD protection shunting component. The ESD protection shunting component is coupled between the I/O pad and a reference node of the integrated circuit. The over-capability detection circuit provides the shut-off signal when safe operating conditions are resumed after a voltage excursion at the I/O pad. After receiving the shut-off signal, the latch biases the ESD protection shunting component into an off-state.Type: GrantFiled: September 25, 2015Date of Patent: June 27, 2017Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: John Eric Kunz, Jr., Jonathan Scott Brodsky
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Patent number: 9629294Abstract: An ESD monitor device may take the form of an integrated circuit with a plurality of monitor components available at each I/O site of the ESD monitor device. Each monitor component has a physical structure which provides scalable ESD robustness. The monitor components are connected in parallel to an ESD bus. An integrated circuit may be formed by processing an ESD monitor device through one or more process steps of an integrated circuit manufacturing line, and subsequently measuring the ESD monitor device. Parameters of a process step of the manufacturing line may be adjusted to reduce ESD events at the process step, based on measurement results from the ESD monitor device. The integrated circuit may subsequently be processed through the adjusted process step.Type: GrantFiled: December 10, 2013Date of Patent: April 18, 2017Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: John Eric Kunz, Jr., Jonathan Scott Brodsky, Gianluca Boselli
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Patent number: 9431384Abstract: An electrostatic discharge (ESD) protection circuit (FIG. 5A) for an integrated circuit is disclosed. The integrated circuit includes a first ESD cell having a current path coupled between a first terminal and a second terminal. A second ESD cell has a current path coupled between the second terminal and a power supply terminal. A passive circuit is connected in parallel with one of the first and second ESD cells.Type: GrantFiled: March 21, 2014Date of Patent: August 30, 2016Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Farzan Farbiz, John Eric Kunz, Jr., Aravind C. Appaswamy, Akram A. Salman
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Publication number: 20160156176Abstract: An electrostatic discharge (ESD) protection circuit includes a substrate having a semiconductor surface that the ESD protection circuit formed thereon. A first ESD cell is stacked in series with at least a second ESD cell. An active shunt transistor is electrically in parallel with the first ESD cell or second ESD cell, where the active shunt includes a control node. A trigger circuit has a trigger input and a trigger output, wherein the trigger output is coupled to the control node.Type: ApplicationFiled: December 2, 2014Publication date: June 2, 2016Inventors: JOHN ERIC KUNZ, JR., FARZAN FARBIZ, ARAVIND C. APPASWAMY, AKRAM A. SALMAN
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Patent number: 9337653Abstract: An integrated circuit with either a normally open MEMS ESD protection switch coupled between a bond pad and an internal circuit or a normally closed MEMS ESD protection switch coupled between the bond pad and a common reference of the integrated circuit. At least one of a control bond pad and an enable logic circuit is coupled to a control terminal of the MEMS ESD protection switch.Type: GrantFiled: August 14, 2013Date of Patent: May 10, 2016Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Jonathan Scott Brodsky, John Eric Kunz, Jr.
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Publication number: 20160020607Abstract: An integrated circuit may include an over-capability detection circuit coupled to an I/O pad which provides a shut-off signal to a latch controlling an ESD protection shunting component. The ESD protection shunting component is coupled between the I/O pad and a reference node of the integrated circuit. The over-capability detection circuit provides the shut-off signal when safe operating conditions are resumed after a voltage excursion at the I/O pad. After receiving the shut-off signal, the latch biases the ESD protection shunting component into an off-state.Type: ApplicationFiled: September 25, 2015Publication date: January 21, 2016Inventors: John Eric Kunz, JR., Jonathan Scott Brodsky
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Patent number: 9213048Abstract: Adapters for electrostatic discharge probe tips are disclosed herein. An embodiment of the adapter includes an attachment device that is attachable to the tip of the probe. A first conductor is affixed to the attachment device so that the first conductor contacts the tip when the attachment device is attached to the tip of the probe. A second conductor extends between the first electrical conductor and a point external to the attachment device.Type: GrantFiled: August 2, 2012Date of Patent: December 15, 2015Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Robert Matthew Mertens, John Eric Kunz, Jr.
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Patent number: 9172243Abstract: An integrated circuit may include an over-capability detection circuit coupled to an I/O pad which provides a shut-off signal to a latch controlling an ESD protection shunting component. The ESD protection shunting component is coupled between the I/O pad and a reference node of the integrated circuit. The over-capability detection circuit provides the shut-off signal when safe operating conditions are resumed after a voltage excursion at the I/O pad. After receiving the shut-off signal, the latch biases the ESD protection shunting component into an off-state.Type: GrantFiled: December 10, 2013Date of Patent: October 27, 2015Assignee: TEXAS INSTRUMENTS CORPORATEDInventors: John Eric Kunz, Jr., Jonathan Scott Brodsky
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Publication number: 20150270253Abstract: An electrostatic discharge (ESD) protection circuit (FIG. 5A) for an integrated circuit is disclosed. The integrated circuit includes a first ESD cell having a current path coupled between a first terminal and a second terminal. A second ESD cell has a current path coupled between the second terminal and a power supply terminal. A passive circuit is connected in parallel with one of the first and second ESD cells.Type: ApplicationFiled: March 21, 2014Publication date: September 24, 2015Applicant: Texas Instruments IncorporatedInventors: Farzan Farbiz, John Eric Kunz, JR., Aravind C. Appaswamy, Akram A. Salman
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Publication number: 20140184237Abstract: An ESD monitor device may take the form of an integrated circuit with a plurality of monitor components available at each I/O site of the ESD monitor device. Each monitor component has a physical structure which provides scalable ESD robustness. The monitor components are connected in parallel to an ESD bus. An integrated circuit may be formed by processing an ESD monitor device through one or more process steps of an integrated circuit manufacturing line, and subsequently measuring the ESD monitor device. Parameters of a process step of the manufacturing line may be adjusted to reduce ESD events at the process step, based on measurement results from the ESD monitor device. The integrated circuit may subsequently be processed through the adjusted process step.Type: ApplicationFiled: December 10, 2013Publication date: July 3, 2014Inventors: John Eric KUNZ, JR., Jonathan Scott BRODSKY, Gianluca BOSELLI
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Publication number: 20140185168Abstract: An integrated circuit may include an over-capability detection circuit coupled to an I/O pad which provides a shut-off signal to a latch controlling an ESD protection shunting component. The ESD protection shunting component is coupled between the I/O pad and a reference node of the integrated circuit. The over-capability detection circuit provides the shut-off signal when safe operating conditions are resumed after a voltage excursion at the I/O pad. After receiving the shut-off signal, the latch biases the ESD protection shunting component into an off-state.Type: ApplicationFiled: December 10, 2013Publication date: July 3, 2014Inventors: John Eric KUNZ, JR., Jonathan Scott BRODSKY
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Patent number: 8760829Abstract: An apparatus comprises a first PFET including a first intrinsic body diode; an electrostatic discharge (ESD) subcircuit coupled to a source of the first PFET; a reverse bias voltage element, such as a zener diode, an anode of which is coupled to a gate of the first PFET; a second PFET having a source coupled to a cathode of the zener diode a capacitor coupled to a gate the second PFET; and a first resistor coupled to the gate of the second PFET. The apparatus can protect against both positive and negative electro static transient discharge events.Type: GrantFiled: April 2, 2012Date of Patent: June 24, 2014Assignee: Texas Instruments IncorporatedInventors: Liang Wang, Weibiao Zhang, Dening Wang, John Eric Kunz, Jr.
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Publication number: 20140049864Abstract: An integrated circuit with either a normally open MEMS ESD protection switch coupled between a bond pad and an internal circuit or a normally closed MEMS ESD protection switch coupled between the bond pad and a common reference of the integrated circuit. At least one of a control bond pad and an enable logic circuit is coupled to a control terminal of the MEMS ESD protection switch.Type: ApplicationFiled: August 14, 2013Publication date: February 20, 2014Applicant: Texas Instruments IncorporatedInventors: Jonathan Scott BRODSKY, John Eric KUNZ, JR.
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Publication number: 20140035608Abstract: Adapters for electrostatic discharge probe tips are disclosed herein. An embodiment of the adapter includes an attachment device that is attachable to the tip of the probe. A first conductor is affixed to the attachment device so that the first conductor contacts the tip when the attachment device is attached to the tip of the probe. A second conductor extends between the first electrical conductor and a point external to the attachment device.Type: ApplicationFiled: August 2, 2012Publication date: February 6, 2014Applicant: Texas Instruments IncorporatedInventors: Robert Matthew Mertens, John Eric Kunz, JR.
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Publication number: 20130264640Abstract: A method of forming a drain extended metal-oxide-semiconductor (MOS) transistor includes forming a gate structure including a gate electrode on a gate dielectric on a semiconductor surface portion of a substrate. The semiconductor surface portion has a first doping type. A source is formed on one side of the gate structure having a second doping type. A drain is formed including a highly doped portion on another side of the gate structure having the second doping type. A masking layer is formed on a first portion of a surface area of the highly doped drain portion. A second portion of the surface area of the highly doped drain portion does not have the masking layer. Selectively siliciding is used to form silicide on the second portion. The masking layer blocks siliciding on the first portion so that the first portion is silicide-free.Type: ApplicationFiled: April 6, 2012Publication date: October 10, 2013Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: AKRAM A. SALMAN, FARZAN FARBIZ, ARAVIND C. APPASWAMY, JOHN ERIC KUNZ, JR., GIANLUCA BOSELLI
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Publication number: 20130188286Abstract: An apparatus comprises a first PFET including a first intrinsic body diode; an electrostatic discharge (ESD) subcircuit coupled to a source of the first PFET; a reverse bias voltage element, such as a zener diode, an anode of which is coupled to a gate of the first PFET; a second PFET having a source coupled to a cathode of the zener diode a capacitor coupled to a gate the second PFET; and a first resistor coupled to the gate of the second PFET. The apparatus can protect against both positive and negative electro static transient discharge events.Type: ApplicationFiled: April 2, 2012Publication date: July 25, 2013Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: Liang Wang, Weibiao Zhang, Dening Wang, John Eric Kunz, JR.
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Publication number: 20080316659Abstract: A protection circuit is disclosed that protects a semiconductor device from damage due to an electrostatic discharge. One such protection circuit comprises a vertical pnp hetero-junction bipolar transistor (HBT) connected between terminals such as supply terminals of the device, configured to conduct during an electrostatic discharge. The protection circuit also comprises a trigger circuit, such as a transient activated RC circuit connected between the terminals to detect the electrostatic discharge and control the transistor based on the detected electrostatic discharge. A Darlington transistor pair in the trigger circuit can be used to multiply the effective capacitance and HBT drive current. The HBT transistor absorbs energy from the electrostatic discharge and clamps the over-voltage across the terminals. The protection circuit may also be used across other I/O terminals of the device.Type: ApplicationFiled: June 19, 2007Publication date: December 25, 2008Inventors: Ismail Hakki Oguzman, John Eric Kunz, JR.