Abstract: A graphics processing unit can queue a large number of texture requests to balance out the variability of texture requests without the need for a large texture request buffer. A dedicated texture request buffer queues the relatively small texture commands and parameters. Additionally, for each queued texture command, an associated set of texture arguments, which are typically much larger than the texture command, are stored in a general purpose register. The texture unit retrieves texture commands from the texture request buffer and then fetches the associated texture arguments from the appropriate general purpose register. The texture arguments may be stored in the general purpose register designated as the destination of the final texture value computed by the texture unit. Because the destination register must be allocated for the final texture value as texture commands are queued, storing the texture arguments in this register does not consume any additional registers.

Abstract: Apparatuses and methods are presented for a hierarchical processor. The processor comprises, at a first level of hierarchy, a plurality of similarly structured first level components, wherein each of the plurality of similarly structured first level components includes at least one combined function module capable of performing multiple classes of graphics operations, each of the multiple classes of graphics operations being associated with a different stage of graphics processing.

Abstract: A graphics pipeline has at least one stage that determines operations to be performed on graphics data based at least in part on data processing attributes associated with the graphics data. One application is to permit one or more operations in a stage to be bypassed. Another application is a multi-function stage in which the data operations that are performed depend at least in part on the data type.

Abstract: An apparatus and method for simulating a multi-ported memory using lower port count memories as banks. A collector units gather source operands from the banks as needed to process program instructions. The collector units also gather constants that are used as operands. When all of the source operands needed to process a program instruction have been gathered, a collector unit outputs the source operands to an execution unit while avoiding writeback conflicts to registers specified by the program instruction that may be accessed by other execution units.

Abstract: A processor buffers asynchronous threads. Current instructions requiring operations provided by a plurality of execution units are divided into phases, each phase having at least one math operation and at least one texture cache access operation. Instructions within each phase are qualified and prioritized, with texture cache access operations in a subsequent phase not qualified until all of the texture cache access operations in a current phase have completed. The instructions may be qualified based on the status of the execution unit needed to execute one or more of the instructions. The instructions may also be qualified based on an age of each instruction, a divergence potential, locality, thread diversity, and resource requirements. Qualified instructions may be prioritized based on execution units needed to execute current instructions and the execution units in use. One or more of the prioritized instructions is issued per cycle to the plurality of execution units.

Abstract: One embodiment of a computing system configured to manage divergent threads in a thread group includes a stack configured to store at least one token and a multithreaded processing unit. The multithreaded processing unit is configured to perform the steps of fetching a program instruction, determining that the program instruction is not a branch instruction, determining whether the program instruction includes a pop-synchronization bit, and updating an active program counter, where the fashion in which the active program counter is updated relates to whether the program instruction includes a pop-synchronization bit.

Abstract: An apparatus and method for simulating a multiported memory using lower port count memories as banks. A portion of memory is allocated for storing data associated with a thread. The portion of memory allocated to a thread may be stored in a single bank or in multiple banks. A collector unit coupled to each bank gathers source operands needed to process a program instruction as the source operands output from one or more banks. The collector unit outputs the source operands to an execution unit when all of the source operands needed to process the program instruction have been gathered.

Abstract: A processing unit includes multiple execution pipelines, each of which is coupled to a first input section for receiving input data for pixel processing and a second input section for receiving input data for vertex processing and to a first output section for storing processed pixel data and a second output section for storing processed vertex data. The processed vertex data is rasterized and scan converted into pixel data that is used as the input data for pixel processing. The processed pixel data is output to a raster analyzer.

Abstract: A method for processing divergent samples in a programmable graphics processing unit is described. In one embodiment, the method includes the step of incrementing a subroutine depth of a first sample to designate that first call instructions are to be executed on the first sample. The method also includes the steps of pushing state data of a second sample upon which the first call instructions are not to be executed onto a global stack and executing the first call instructions on the first sample.

Abstract: Instruction dispatch in a multithreaded microprocessor such as a graphics processor is not constrained by an order among the threads. Instructions are fetched into an instruction buffer that is configured to store an instruction from each of the threads. A dispatch circuit determines which instructions in the buffer are ready to execute and may issue any ready instruction for execution. An instruction from one thread may be issued prior to an instruction from another thread regardless of which instruction was fetched into the buffer first. Once an instruction from a particular thread has issued, the fetch circuit fills the available buffer location with the following instruction from that thread.

Abstract: A system, method and computer program product are provided for programmable pixel processing in a computer graphics pipeline. In one embodiment of the present invention, arbitrary texture filtering is applied via a programmable shader.

Abstract: A fragment program may configure a fragment shader to compute a destination position for a fragment, where the destination position is independent of a position computed for the fragment during rasterization of a primitive. The destination position may be computed based on fragment parameters such as color, depth, and transparency. A raster operation unit writes processed fragment data to the destination position. Furthermore, the fragment program may configure the fragment shader to compute a per-fragment stencil operation for use by the raster operation unit during stencil buffering.

Abstract: System and method for reserving a memory space for multithreaded processing is described. Memory space within a memory resource is allocated responsive to thread type. Examples of thread types for graphics processing include primitive, vertex and pixel types. Memory space allocated may be of a predetermined size for a thread type. Memory locations within a first memory space may be interleaved with memory locations within a second memory space.

Abstract: A system, method and article of manufacture are provided for programmable processing in a computer graphics pipeline. Initially, data is received from a source buffer. Thereafter, programmable operations are performed on the data in order to generate output. The operations are programmable in that a user may utilize instructions from a predetermined instruction set for generating the same. Such output is stored in a register. During operation, the output stored in the register is used in performing the programmable operations on the data.

Abstract: A central processing unit (CPU) including an operating system for executing code segments capable of performing graphics processing on the CPU. Associated therewith is a graphics application specific integrated circuit (ASIC) for performing graphics processing in accordance with a graphics processing standard. An extension to the software is included that identifies a first portion of the graphics processing to be performed on the graphics ASIC and a second portion of the graphics processing to be performed on the CPU. Such second portion of the graphics processing includes application-programmable vertex processing unavailable by the graphics ASIC. A compiler compiles the software to execute the first portion of the graphics processing on the graphics ASIC and the second portion of the graphics processing on the CPU in accordance with the extension.

Abstract: A system, method and computer program product are provided for texture shading in a hardware graphics processor. Initially, a plurality of texture coordinates is identified. Further, it is determined whether a hardware graphics processor is operating in a texture shader mode. If the hardware graphics processor is operating in the texture shader mode, the texture coordinates are mapped to colors utilizing a plurality of texture shader stages in the hardware graphics processor. If, however, the hardware graphics processor is not operating in the texture shader mode, the texture coordinates are mapped to colors utilizing a conventional graphics application program interface (API) in conjunction with the hardware graphics processor.

Abstract: Method and interface for sending vertex data output from a vertex processing unit to memory is described. Conventionally, the vertex data output is not output directly to memory via a dedicated write interface, but is instead passed through downstream computation units in a graphics processor and written to memory via the write interface normally used to write pixel data. When the downstream computation units are configured to pass the vertex data output through unmodified, processing of the vertex data output by the downstream computation units is deferred until a second pass through those units. When the vertex data output is output directly to memory, processing of the vertex data output by the downstream computation units can be initiated during a first pass through those units.

Abstract: Apparatuses and methods for detecting position conflicts during fragment processing are described. Prior to executing a program on a fragment, a conflict detection unit, within a fragment processor checks if there is a position conflict indicating a RAW (read after write) hazard may exist. A RAW hazard exists when there is a pending write to a destination location that source data will be read from during execution of the program. When the fragment enters a processing pipeline, each destination location that may be written during the processing of the fragment is entered in conflict detection unit. During processing, the conflict detection unit is updated when a pending write to a destination location is completed.

Abstract: A system, method and computer program product are provided for programmable pixel processing in a computer graphics pipeline. In one embodiment of the present invention, a computed arbitrary quantity is applied as texture address.

Abstract: A method and system for implementing programmable texture lookups from texture coordinate sets. The method includes the step of generating a plurality of texture coordinates using a shader module. The shader module executes floating point calculations on received pixel data to generate the texture coordinates. A plurality of texture values are fetched using the texture coordinates. The fetching is performed by a texture unit coupled to receive the texture coordinates from the shader module. The fetching of the texture values is programmable with respect to the texture coordinates such that the number of texture coordinates are decoupled from the number of textures.