Abstract: An integrated circuit (203) for use in processing streams of data generally and streams of packets in particular. The integrated circuit (203) includes a number of packet processors (307, 313, 303), a table look up engine (301), a queue management engine (305) and a buffer management engine (315). The packet processors (307, 313, 303) include a receive processor (421), a transmit processor (427) and a risc core processor (401), all of which are programmable. The receive processor (421) and the core processor (401) cooperate to receive and route packets being received and the core processor (401) and the transmit processor (427) cooperate to transmit packets. Routing is done by using information from the table look up engine (301) to determine a queue (215) in the queue management engine (305) which is to receive a descriptor (217) describing the received packet's payload.

Abstract: An integrated circuit (203) for use in processing streams of data generally and streams of packets in particular. The integrated circuit (203) includes a number of packet processors (307, 313, 303), a table look up engine (301), a queue management engine (305) and a buffer management engine (315). The packet processors (307, 313, 303) include a receive processor (421), a transmit processor (427) and a risc core processor (401), all of which are programmable. The receive processor (421) and the core processor (401) cooperate to receive and route packets being received and the core processor (401) and the transmit processor (427) cooperate to transmit packets. Routing is done by using information from the table look up engine (301) to determine a queue (215) in the queue management engine (305) which is to receive a descriptor (217) describing the received packet's payload.

Abstract: A macropipelined microprocessor chip adheres to strict read and write ordering by sequentially buffering operands in queues during instruction decode, then removing the operands in order during instruction execution. Any instruction that requires additional access to memory inserts the requests into the queued sequence (in a specifier queue) such that read and write ordering is preserved. A specifier queue synchronization counter captures synchronization points to coordinate memory request operations among the autonomous instruction decode unit, instruction execution unit, and memory sub-system. The synchronization method does not restrict the benefit of overlapped execution in the pipelined. Another feature is treatment of a variable bit field operand type that does not restrict the location of operand data. Instruction execution flows in a pipelined processor having such an operand type are vastly different depending on whether operand data resides in registers or memory.

Abstract: A mud pressure intensifier works with existing conventional drill strings without requiring special equipment or drilling fluids. The intensifier is self-contained and is located in the drill string between the drill bit and the rest of the string. The rotational power generated by a conventional mud motor is converted into reciprocal action to reciprocate a piston. The piston elevates the pressure of a portion of the mud on both the upstroke and the downstroke before discharging the pressurized mud at the drill bit.

Abstract: In a well using a lift pump operated by a tension string from the surface, the down stroke of the pump is accelerated by providing a plunger element secured to the pump operating string. The plunger has an upper end exposed to the high hydrostatic pressure in the tubing string above the pump, and a lower end exposed to the substantially lower hydrostatic pressure in the well outside the tubing string. This produces a net downwards force on the pump operating string allowing a higher pump speed and a higher volume delivery.

Abstract: The present invention provides a personal, portable and self-powered ultraviolet light intensity (UVI) monitor and a method for determining the duration of safe exposure to the sun or, alternatively, the value of the sun protection factor (SPF) of a sun protection product required for a given duration of exposure to the sun. The monitor is a substrate imprinted with indicia and non-uniformly overlaid with photosensitive material. Depending on the intensity of UV light to which the monitor is exposed, the photosensitive material changes physical characteristics and exposes some and conceals other indicia to indicate a duration of safe exposure to the sun for given conditions or the SPF value of the sun protection product used to be used, or both.

Abstract: A method for removing fines, such as sand, from a crude oil tank generally includes the steps of directing a fluid into the bottom of the tank to stir up the sand settled therein to create a sand and fluid slurry. The method further includes the step of suctioning the slurry from the tank. To accomplish the steps, a pressure line is coupled to a pump which jettisons fluid through holes in the pressure line located near the bottom of the oil tank to stir the fines, thereby creating a slurry. A drain line is also located near the bottom of the tank, and is coupled to another pump for simultaneously suctioning the slurry through the drain line outside of the tank. A gravel or dump truck, or the like, is retrofitted with the pressure line and drain line pumps and tubing adapted to couple the drain line to the bed of the truck so that the slurry is extracted from the tank through the drain line into the bed of the truck.

Abstract: A method of specifying the operands for a microcoded CPU employs a combination of a set of microinstruction routines for generic operand modes, along with hardware primitives for selecting various specific types of operand treatment. Decoding of a machine-level instruction produces an entry point for the microstore, selecting one of the set of generic operand modes. Also, decoding of the instruction produces control bits that are used directly to select the specific operand type or used by the hardware primitives. In this way, branching is avoided in the microinstruction sequences used for operand specifying, but yet the amount of microcode needed is a minimum.

Abstract: A data dependency scoreboard for a pipelined digital computer includes a source counter and a destination counter for each general purpose register (GPR). The source counter for each GPR is incremented each time that a specifier is decoded that specifies the use of the source counter's GPR as a source operand. The source counter is decremented each time that an execution unit reads a source operand from the source counter's GPR. The destination counter is incremented each time that a specifier is decoded that specifies the use of the counter's GPR as a destination operand. The destination counter is decremented each time that the execution unit writes to the destination counter's GPR. A data dependency conflict causing a complex specifier unit to stall occurs when operand processing requires a write to a GPR that has a source counter value greater than zero, and when operand processing requires a read of a GPR that has a destination counter value greater than zero.

Abstract: In a well using a lift pump operated by a tension string from the surface, the down stroke of the pump is accelerated by providing a plunger element secured to the pump operating string. The plunger has an upper end exposed to the high hydrostatic pressure in the tubing string above the pump, and a lower end exposed to the substantially lower hydrostatic pressure in the well outside the tubing string. This produces a net downwards force on the pump operating string allowing a higher pump speed and a higher volume delivery.

Abstract: A system for evaluating the performance of a computer system having a processor that passes through a plurality of processor states during operation and an associated system memory includes an operating unit for receiving a request to monitor specific process states from a user. Firmware causes the processor to enter the desired processor state requested by the user. The hardware identifies the occurrence of the desired processor state. Information relating to the occurrence of the desired process state is accumulated the memory. The accumulated information is read from memory and a report is provided to the user.

Abstract: A pipelined processor has an instruction unit for decoding instructions and pre-processing operands prior to instruction execution, and an execution unit for executing the decoded instructions. The pre-processing of operands includes changes to general purpose registers, and the changes are recorded in an RLOG queue having read and write pointers. Instruction context for the RLOG queue entries is maintained in a separate RLOG base queue. When decoding begins for a new instruction, the RLOG base queue is loaded with the RLOG write pointer to the first RLOG queue entry that would record a register change for that next instruction. Each time an operand is processed that changes a general purpose register, the value of the change is recorded in the entry pointed to by the RLOG queue write pointer, and the RLOG queue write pointer is advanced.

Abstract: A pipelined CPU executes instructions of variable length, and references memory using various data widths. Macroinstruction pipelining is employed (instead of microinstruction pipelining), with queueing between units of the CPU to allow flexibility in instruction execution times. A branch prediction method employs a branch history table which records the taken vs. not-taken history of branch opcodes recently used, and uses an empirical aglorithm to predict which way the next occurrence of this branch will go, based upon the history table. The branch history table stores in each entry a number of bits for each branch address, each bits indicating "taken" or "not-taken" for one occurrence of the branch. The table is indexed by branch address. A register stores the empirical aglorithm, and upon occurrence of a branch its history is fetched from the table and used to select a location in the register containing a prediction for this particular pattern of branch history.

Abstract: A pipelined CPU employs separate microinstruction pipelines for the execution unit and memory management unit. Deadlocks can occur in a pipelined CPU when there is data dependency in two consecutive instructions. The later instruction may stall the pipeline if operands fetched by an earlier instruction are needed, but the earlier instruction is not producing the memory request for the operands because the pipeline is stalled; this results in a deadlock. Using separate micro-pipelines, the earlier instruction is advanced independently of the rest of the pipeline, in the case of a deadlock, so that the operands for the later instruction are provided and the deadlock is broken.

Abstract: Pipelined CPUs achieve high-performance by fine tuning the pipe stages to execute typical instruction sequences. Atypical instruction sequences result in pipeline exceptions. The disclosed method provides graceful exception handling and recovery in a micropipelined memory interface. The use of a memory reference restart command latch allows an implementation that requires no additional logic for conditional writing of states pending exception checking. The exception handling hardware is minimized because instructions which cause exceptions are never re-executed, and exception handling microcode executes in-line with the normal microcode flow.

Abstract: A method of forming thick film resistor circuits whereby a non-hole metal, such as copper, requiring a reducing atmosphere is included with resistor material requiring an oxidizing atmosphere. A fritless conductor paste with a small percentage of silver is deposited and fired in air at a low temperature. Resistors are then deposited and fired in air. Subsequently, the conductor material is reduced at a sufficiently low temperature so as not to adversely affect the resistors.

Abstract: A method is provided for effecting the removal of polychlorinated biphenyls from hydrocarbon oils, such as transformer oil, contaminated with more than 50 ppm of such polychlorinated biphenyls. There is utilized in the contaminated oil, while it is being agitated, dispersed metallic sodium, an aprotic ion-complexing solvent, for example, diglyme, and an oil-soluble electron carrier, such as naphthalene.

Abstract: A method of forming thick film resistor circuits whereby non-noble metals (11, 12) requiring a reducing firing atmosphere are included with resistor material (13) requiring an oxidizing atmosphere. The conductor metallization is capable of adhering to the substrate at a low firing temperature in air. The resistors are printed and fired in air after conductor formation. The metal oxide can then be reduced at a sufficiently low temperature so as not to significantly affect the resistor material. In one embodiment, the conductor paste includes copper and glass frits which can adhere to a ceramic substrate by firing at a temperature of less than 1100 degrees C.