Abstract: A solid electrolyte capacitor cell includes a cathode contact layer, a cathode layer of carbon and RbAg.sub.4 I.sub.5 surrounded by a peripheral portion of the cathode contact layer, a larger electrolyte layer of RbAg.sub.4 I.sub.5 attached to the cathode layer, and an anode layer of carbon and RbAg.sub.4 I.sub.5, an anode contact layer, and an insulative, annular silver barrier extending between and contacting peripheral portions of the cathode contact layer, the anode contact layer, and edges of the cathode, electrolyte, and anode layers to prevent silver migration. A composite capacitor includes a plurality of the series-connected solid electrolyte cells stacked in an elastic housing that maintains isostatic internal pressure throughout the electrolyte layers of all of the cells, making them resistant to formation of minute cracks in all of the electrolyte layers. This prevents deposition of silver in such cracks during charge/discharge cycling and therefore prevents cathode-to-anode shorts.

Abstract: A technique is disclosed for supplying backup power by providing a solid-state electrochemical capacitor with a layer of solid electrolyte material composed of RbAg.sub.4 I.sub.5, a layer of anode material composed of carbon and RbAg.sub.4 I.sub.5 adjoining a first surface of the electrolyte material, and a layer of cathode material composed of carbon and RbAg.sub.4 I.sub.5 adjoining a second surface of the electrolyte material. A current is supplied to charge the anode of the capacitor structure to a voltage in the range from 0.50 volts to 0.66 volts to cause storage of charge in the capacitor structure in both a double layer capacitance mode and a pseudo capacitance mode. The charged up capacitor is used to supply a backup voltage to a utilization device. In one embodiment, the anode includes a silver disk adjoining the electrolyte layer. In another embodiment, the anode contains platinized activated carbon and RbAg.sub.4 I.sub.5 to reduce silver dendrite growth during charging.

Abstract: A technique is disclosed for supplying backup power by providing a solid-state electrochemical capacitor with a layer of solid electrolyte material composed of RbAg.sub.4 I.sub.5, a layer of anode material composed of carbon and RbAg.sub.4 I.sub.5 adjoining a first surface of the electrolyte material, and a layer of cathode material composed of carbon and RbAg.sub.4 I.sub.5 adjoining a second surface of the electrolyte material. A current is supplied to charge the anode of the capacitor structure to a voltage in the range from 0.50 volts to 0.66 volts to cause storage of charge in the capacitor structure in both a double layer capacitance mode and a pseudo capacitance mode. The charged up capacitor is used to supply a backup voltage to a utilization device. In one embodiment, the anode includes a silver disk adjoining the electrolyte layer. In another embodiment, the anode contains platinized activated carbon and RbAg.sub.4 I.sub.5 to reduce silver dendrite growth during chraging.

Abstract: A technique is disclosed for supplying backup power by providing a solid-state electrochemical capacitor with a layer of solid electrolyte material composed of RbAg.sub.4 I.sub.5, a layer of anode material composed of carbon and RbAg.sub.4 I.sub.5 adjoining a first surface of the electrolyte material, and a layer of cathode material composed of carbon and RbAg.sub.4 I.sub.5 adjoining a second surface of the electrolyte material. A current is supplied to charge the anode of the capacitor structure to a voltage in the range from 0.50 volts to 0.66 volts to cause storage of charge in the capacitor structure in both a double layer capacitance mode and a pseudo capacitance mode. The charged up capacitor is used to supply a backup voltage to a CMOS memory. The capacitor structure is made by compressing the electrolyte, the anode, and the cathode together to produce molecular bonding without binder material, using compression forces of approximately 80,000 psi.

Abstract: A non-volatile memory system includes an SRAM and a backup store of E.sup.2 PROMs. In the event of a short duration power interruption, the memory system enters a hold mode in which data maintenance power is supplied to the SRAM by discharging a backup capacitor, and accessing of the SRAM by a host computer is halted. If the backup capacitor voltage does not fall below a threshold before power is restored, the hold mode is terminated and accessing by the host computer continues. If the backup capacitor voltage falls below the threshold, operating power is supplied to the SRAM, E.sup.2 PROM, and associated circuitry to download all data and row and column parity data into the E.sup.2 PROM by further discharging of the backup capacitor. Row parity and column parity information are accumulated by a bit-per-chip accumulation technique that allows convenient error correction on a "per chip" basis. Data is encrypted and decrypted on the basis of a fully erasable magnetic key.

Abstract: The sense voltages of an NDRO core memory including two cores per memory bit are increased by using a "soft write" technique wherein one of the two ferrite cores of each memory bit is written into by a smaller write current than the other. This results in a steeper slope toward the knee of the lower part of the hysteresis characteristic of the first core. The steeper slope results in a larger induced voltage for the first core. This increases the difference between the induced voltages of the two cores, thereby increasing the sense voltage to be detected by the sense circuitry.

Abstract: A system for optimizing the performance of a bubble memory includes a temperature sensor, the output of which is amplified and converted to a digital number by a low power A/D converter to address a memory that stores correction data for various temperatures represented by the temperature sensor output. The correction data output by the memory is converted to an analog signal that is used to control the current flowing through a bias coil of the bubble memory. The bubble memory is used as a non-volatile back-up memory for a CMOS-RAM. A relatively small capacitor bank is charged to a high voltage during normal operation of the CMOS-RAM by a voltage booster circuit. In the event of a power interruption, low power control circuitry actuates a voltage down converter circuit that produces a regulated output voltage to temporarily power the control circuitry while the CMOS-RAM is being transferred to the bubble memory.

Abstract: A core memory system includes a plurality of word lines strung through a core memory array and a plurality of field effect transistors coupling respective ones of the word select lines to an address decoding circuit. In one embodiment of the invention, the field effect transistors are utilized in conjunction with a transformer selection system. In the transformer selection system, the drain electrodes of each field effect transistor are connected in series with respective ones of a plurality of secondary windings of a transformer. The system includes a plurality of such transformers, the primary windings of the various transformers being selected in response to a first decoder. The gates of the respective field effect transistors are selected in response to a second decoder.

Abstract: A core memory system includes an array of toroidal ferrite cores, and also includes two hundred fifty-six X lines extending through a plurality of the cores, one hundred twenty-eight Y lines extending through a plurality of the cores, and eighteen sense-inhibit lines, each extending through a respective plurality of the cores. The X lines are organized as 16 groups, the first ends of all X lines in each respective group being electrically connected together at a common junction. The common junction is connected to a first lead of a first winding of a Balun transformer. The Balun transformer includes 17 identical windings about a toroidal core. The second end of the first winding is connected to the output of an address driver/receiver circuit. The second ends of each of the 16 X lines are connected to the second leads of respective ones of the remaining 16 windings of the Balun transformer. The second leads of each of the 16 windings are connected to respective address driver/receiver circuits.