Abstract: The invention employs an execution control unit consisting of a look up memory, three instruction registers and logic gates to control pipe line processing by an ALU. During such processing the sequential steps required to execute a program instruction are overlapped so that the ALU and its associated memory are always busy. The three instruction registers are provided to receive and retain up to three instructions which may be in process at a given time. The memory is preferably divided into a plurality of banks to improve the performance of the system by reducing the occurrence of a memory busy condition. To facilitate pipe lining an instruction format is employed having a fixed location for the data field which specifies the register to be used for address preparation.

Abstract: Partitioning, paging, and segmentation techniques are employed with virtual memory to provide more secure and efficient storage and transfer of information. The virtual memory is divided into a plurality of partitions with real memory storage provided by paging the plurality of partitions. User programs are segmented into logical units and stored in assigned partitions thereby isolating user programs and data. Unsegmented programs may be run by storage in a partition with direct addressing. Segment descriptors including partition, base, and bound are utilized in accessing memory. User domains are expandable by temporarily passing descriptor parameters from one routine to another with access flags limiting access thereto. By shrinking passed descriptors the receiving routine can be restricted to only a portion of the information defined by the descriptor.

Abstract: In a data processing system employing paging and segmentation for storing information in memory, the input-output unit is provided with addressing capability for addressing and accessing memory without the intervention of the central processing unit to convert virtual addresses to absolute addresses. Paged tables are set up in memory by the central processing unit prior to input-output operations containing page table words, and a page table is assigned to each peripheral. A peripheral control word assigned to each peripheral includes a pointer to the start of the peripheral's page table whereby the peripheral through the I/O unit and without central processing intervention can locate its assigned page table, and page table words therein are used independent of any central processor virtual to absolute address conversion to access paged memory locations.