Abstract: An out-of-order and speculative execution microprocessor that mitigates side channel attacks includes a cache memory and fill request generation logic that generates a request to fill the cache memory with a cache line implicated by a memory address that misses in the cache memory. At least one execution pipeline receives first and second load operations, detects a condition in which the first load generates a need for an architectural exception, the second load misses in the cache memory, and the second load is newer in program order than the first load, and prevents state of the cache memory from being affected by the miss of the second load by inhibiting the fill request generation logic from generating a fill request for the second load or by canceling the fill request for the second load if the fill request generation logic has already generated the fill request for the second load.

Abstract: A data cache memory mitigates side channel attacks in a processor that comprises the data cache memory and that includes a translation context (TC). A first input receives a virtual memory address. A second input receives the TC. Control logic, with each allocation of an entry of the data cache memory, uses the received virtual memory address and the received TC to perform the allocation of the entry. The control logic also, with each access of the data cache memory, uses the received virtual memory address and the received TC in a correct determination of whether the access hits in the data cache memory. The TC includes a virtual machine identifier (VMID), or a privilege mode (PM) or a translation regime (TR), or both the VMID and the PM or the TR.

Abstract: A physically-tagged data cache memory mitigates side channel attacks by using a translation context (TC). With each entry allocation, control logic uses the received TC to perform the allocation, and with each access uses the received TC in a hit determination. The TC includes an address space identifier (ASID), virtual machine identifier (VMID), a privilege mode (PM) or translation regime (TR), or combination thereof. The TC is included in a tag of the allocated entry. Alternatively, or additionally, the TC is included in the set index to select a set of entries of the cache memory. Also, the TC may be hashed with address index bits to generate a small tag also included in the allocated entry used to generate an access early miss indication and way select.

Abstract: A superscalar out-of-order speculative execution microprocessor mitigates side channel attacks that attempt to exploit speculation windows within which instructions dependent in their execution upon a result of a load instruction may speculatively execute before being flushed because the load instruction raises an architectural exception. A load unit signals an abort request, among other potential abort requests, to control logic in response to detecting that a load instruction causes a need for an architectural exception. The control logic initiates an abort process as soon as the control logic determines that the abort request from the load unit is highest priority among any other concurrently received abort requests and determines a location of the exception-causing load instruction within the program order of outstanding instructions. To perform the abort process, the control logic flushes from the pipeline all instructions dependent upon a result of the exception-causing load instruction.

Abstract: A microprocessor that mitigates side channel attacks includes a front end that processes instructions in program order and a back end that performs speculative execution of instructions out of program order in a superscalar fashion. Producing execution units produce architectural register results during execution of instructions. Consuming execution units consume the produced architectural register results during execution of instructions. The producing and consuming execution units may be the same or different execution units. Control logic detects that, during execution by a producing execution unit, an architectural register result producing instruction causes a need for an architectural exception and consequent flush of all instructions younger in program order than the producing instruction and prevents all instructions within the back end that are dependent upon the producing instruction from consuming the architectural register result produced by the producing instruction.

Abstract: A processor for mitigating side channel attacks includes units that perform fetch, decode, and execution of instructions and pipeline control logic. The processor performs speculative and out-of-order execution of the instructions. The units detect and notify the control unit of events that cause a change from a first translation context (TC) to a second TC. In response, the pipeline control logic prevents speculative execution of instructions that are dependent in their execution on the change to the second TC until all instructions that are dependent on the first TC have completed execution, which may involve stalling their dispatch until all first-TC-dependent instructions have at least completed execution, or by tagging them and dispatching them to execution schedulers but preventing them from starting execution until all first-TC-dependent instructions have at least completed execution.

Abstract: A processor and a method are disclosed that mitigate side channel attacks (SCAs) that exploit store-to-load forwarding operations. In one embodiment, the processor detects a translation context change from a first translation context (TC) to a second TC and responsively disallows store-to-load forwarding until all store instructions older than the TC change are committed. The TC comprises an address space identifier (ASID), a virtual machine identifier (VMID), a privilege mode (PM) or a combination of two or more of the ASID, VMID and PM, or a derivative thereof, such as a TC hash, TC generation value, or a RobID associated with the last TC-updating instruction. In other embodiments, TC generation values of load and store instructions are compared or RobIDs of the load and store instructions are compared with the RobID associated with the last TC-updating instruction. If the instructions' RobIDs straddle the TC boundary, store-to-load forwarding is not allowed.

Abstract: In order to mitigate side channel attacks that exploit speculative store-to-load forwarding, a store dependence predictor is used to prevent store-to-load forwarding if the load and store instructions do not have a matching translation context (TC). In one design, a store queue (SQ) stores the TC—a function of the privilege mode (PM), address space identifier (ASID), and/or virtual machine identifier (VMID)—of each store and conditions store-to-load forwarding on matching store and load TCs. In another design, a memory dependence predictor (MDP) disambiguates predictions of store-to-load forwarding based on the load instruction's TC. In each design, the MDP or SQ does not predict or allow store-to-load forwarding for loads whose addresses, but not their TCs, match an MDP entry.

Abstract: A processor is disclosed that mitigates side channel attacks that exploit speculative store-to-load forwarding. The processor includes logic that conditions store-to-load forwarding of uncommitted store data in the store queue from an uncommitted store instruction to the load instruction upon circumstances associated with a translation context (TC) change or update. The TC comprises an address space identifier (ASID), a virtual machine identifier (VMID), a privilege mode (PM) or a combination of two or more of the ASID, VMID and PM or a derivative thereof. The logic is embedded or associated with any of several structures, such as a store queue (SQ), a memory dependence predictor (MDP), or a reorder buffer (ROB).

Abstract: A digital processor stores pointers of different sizes in memory. The processor, specifically, executes instructions to store a long or short pointer. Long pointers reference any address in the memory's logical address space, while short pointers merely reference any address in a subset of that space. However, short pointers are smaller in size as stored in memory than long pointers. Long pointers thus support relatively large address range capabilities, while short pointers use less memory. The processor also executes instructions to load a long or short pointer into the register file, and does so in a way that does not require the processor to distinguish between the different pointers when executing other instructions. Specifically, the processor converts long and short pointers into a common format for loading into the register file, and converts pointers in the common format back into long or short pointers for storing in the memory.

Abstract: A digital processor stores pointers of different sizes in memory. The processor, specifically, executes instructions to store a long or short pointer. Long pointers reference any address in the memory's logical address space, while short pointers merely reference any address in a subset of that space. However, short pointers are smaller in size as stored in memory than long pointers. Long pointers thus support relatively large address range capabilities, while short pointers use less memory. The processor also executes instructions to load a long or short pointer into the register file, and does so in a way that does not require the processor to distinguish between the different pointers when executing other instructions. Specifically, the processor converts long and short pointers into a common format for loading into the register file, and converts pointers in the common format back into long or short pointers for storing in the memory.

Abstract: A method and apparatus for out-of-order processing of packets are described. In one embodiment, the method includes receiving packets in a global order, the packets being designated for different ones of a plurality of reorder contexts. The method also includes, for each of the plurality of reorder contexts, assigning reorder context sequence numbers indicating an order relative to the global order of the packets designated for that reorder context. The method also includes storing packet descriptors for each of the packets in a shared reorder buffer, and completing processing of at least certain of the packets out of the global order. The method also includes, for each of the plurality of reorder contexts, maintaining a first indication of the one of the sequence numbers assigned the one of the packets that is next to be retired for that reorder context.

Abstract: These and other aspects of the present invention will be better described with reference to the Detailed Description and the accompanying figures. A method and apparatus for out-of-order processing of packets using linked lists is described. In one embodiment, the method includes receiving packets in a global order, the packets being designated for different ones of a plurality of reorder contexts. The method also includes storing information regarding each of the packets in a shared reorder buffer. The method also includes for each of the plurality of reorder contexts, maintaining a reorder context linked list that records the order in which those of the packets that were designated for that reorder context and that are currently stored in the shared reorder buffer were received relative to the global order.

Abstract: A method and system for maintaining memory coherence in a trace cache is disclosed. The method and system comprises monitoring a plurality of entries in a trace cache. The method and system includes selectively invalidating at least one trace cache entry based upon detection of a modification of the at least one trace cache entry. If modifications are detected, then corresponding trace cache entries are selectively invalidated (rather than invalidating the entire trace cache). Thus trace cache coherency is maintained with respect to memory in a performance and power-efficient manner. The monitoring further accounts for situations where more than one trace cache entry is dependent on a single cache line, such that modifications to the single cache line result in invalidations of a plurality of trace cache entries.

Abstract: A method and apparatus for processing out-of-order processing of packets is described. In one embodiment, the method includes receiving a packet, which is in an original position relative to other packets; and attempting, by a primary processing unit, to classify and process the packet. The method also includes determining whether the packet was completely classified and processed by the primary processing unit; and upon determining that the primary processing unit completely classified and processed the packet, bypassing a secondary processing unit. The method also includes transmitting the packet onto a network, the packet being transmitted in its original position relative to the other packets.

Abstract: A method and apparatus for out-of-order processing of packets are described. In one embodiment, the method includes receiving packets in a global order, the packets being designated for different ones of a plurality of reorder contexts. The method also includes, for each of the plurality of reorder contexts, assigning reorder context sequence numbers indicating an order relative to the global order of the packets designated for that reorder context. The method also includes storing packet descriptors for each of the packets in a shared reorder buffer, and completing processing of at least certain of the packets out of the global order. The method also includes, for each of the plurality of reorder contexts, maintaining a first indication of the one of the sequence numbers assigned the one of the packets that is next to be retired for that reorder context.

Abstract: These and other aspects of the present invention will be better described with reference to the Detailed Description and the accompanying figures. A method and apparatus for out-of-order processing of packets using linked lists is described. In one embodiment, the method includes receiving packets in a global order, the packets being designated for different ones of a plurality of reorder contexts. The method also includes storing information regarding each of the packets in a shared reorder buffer. The method also includes for each of the plurality of reorder contexts, maintaining a reorder context linked list that records the order in which those of the packets that were designated for that reorder context and that are currently stored in the shared reorder buffer were received relative to the global order.

Abstract: These and other aspects of the present invention will be better described with reference to the Detailed Description and the accompanying figures. A method and apparatus for out-of-order processing of packets using linked lists is described. In one embodiment, the method includes receiving packets in a global order, the packets being designated for different ones of a plurality of reorder contexts. The method also includes storing information regarding each of the packets in a shared reorder buffer. The method also includes for each of the plurality of reorder contexts, maintaining a reorder context linked list that records the order in which those of the packets that were designated for that reorder context and that are currently stored in the shared reorder buffer were received relative to the global order.

Abstract: A method and apparatus for out-of-order processing of packets are described. In one embodiment, the method includes receiving packets in a global order, the packets being designated for different ones of a plurality of reorder contexts. The method also includes, for each of the plurality of reorder contexts, assigning reorder context sequence numbers indicating an order relative to the global order of the packets designated for that reorder context. The method also includes storing packet descriptors for each of the packets in a shared reorder buffer, and completing processing of at least certain of the packets out of the global order. The method also includes, for each of the plurality of reorder contexts, maintaining a first indication of the one of the sequence numbers assigned the one of the packets that is next to be retired for that reorder context.

Abstract: In an embodiment, a method comprises receiving a first instruction and a second instruction, where the second instruction specifies that a destination address of the first instruction should be replaced with a destination address of the second instruction. The method also includes decoding the first instruction and the second instruction. The decoding comprises replacing a destination address of the first instruction with an address provided by the second instruction, upon determining that the second instruction is a suffix instructions to the first instruction.