Patents by Inventor John G. Ferguson
John G. Ferguson has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10929590Abstract: Techniques and mechanisms for the use of layout-versus-schematic (LVS) design tools to validate photonic integrated circuit designs. Various implementations employ alternate analysis techniques with LVS analysis tools to perform one or more LVS analysis processes on photonic integrated circuits. These analysis processes may include curvilinear design validation and the associated flow implementations.Type: GrantFiled: December 12, 2018Date of Patent: February 23, 2021Assignee: Mentor Graphics CorporationInventors: Ruping Cao, John G. Ferguson, John D. Cayo, Alexandre Arriordaz
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Publication number: 20190114384Abstract: Techniques and mechanisms for the use of layout-versus-schematic (LVS) design tools to validate photonic integrated circuit designs. Various implementations employ alternate analysis techniques with LVS analysis tools to perform one or more LVS analysis processes on photonic integrated circuits. These analysis processes may include curvilinear design validation and the associated flow implementations.Type: ApplicationFiled: December 12, 2018Publication date: April 18, 2019Inventors: Ruping Cao, John G. Ferguson, John D. Cayo, Alexandre Arriordaz
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Patent number: 10185799Abstract: Techniques and mechanisms for the use of layout-versus-schematic (LVS) design tools to validate photonic integrated circuit designs. Various implementations employ alternate analysis techniques with LVS analysis tools to perform one or more LVS analysis processes on photonic integrated circuits. These analysis processes may include curvilinear design validation and the associated flow implementations.Type: GrantFiled: April 22, 2015Date of Patent: January 22, 2019Assignee: Mentor Graphics CorporationInventors: Ruping Cao, John G. Ferguson, John D. Cayo, Alexandre Arriordaz
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Patent number: 10089432Abstract: When a designer designates one or more errors identified in layout design data as false errors, waiver geometric elements corresponding to the designated false errors are created and added to the design. The waiver geometric element may be associated with a verification rule that generated its corresponding false error. When the design is subsequently analyzed using those verification rules in another verification rule check process, the waiver geometric elements are examined, and used to mask those errors associated with a waiver geometric element that would otherwise be displayed to the designer. A designer may also designate a waiver region based on pattern matching, cell names or layout markers in which layout region one or more verification rules may be inapplicable. A waiver region identification item for the waiver region may be associated with a waiver geometric element and the one or more verification rules.Type: GrantFiled: November 23, 2011Date of Patent: October 2, 2018Assignee: Mentor Graphics CorporationInventors: John G. Ferguson, Jonathan J. Muirhead, Bikram Garg
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Publication number: 20180260511Abstract: When a designer designates one or more errors identified in layout design data as false errors, waiver geometric elements corresponding to the designated false errors are created and added to the design. The waiver geometric element may be associated with a verification rule that generated its corresponding false error. When the design is subsequently analyzed using those verification rules in another verification rule check process, the waiver geometric elements are examined, and used to mask those errors associated with a waiver geometric element that would otherwise be displayed to the designer. A designer may also designate a waiver region based on pattern matching, cell names or layout markers in which layout region one or more verification rules may be inapplicable. A waiver region identification item for the waiver region may be associated with a waiver geometric element and the one or more verification rules.Type: ApplicationFiled: November 23, 2011Publication date: September 13, 2018Inventors: John G. Ferguson, Jonathan J. Muirhead, Bikram Garg
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Publication number: 20160055289Abstract: Techniques and mechanisms for the use of layout-versus-schematic (LVS) design tools to validate photonic integrated circuit designs. Various implementations employ alternate analysis techniques with LVS analysis tools to perform one or more LVS analysis processes on photonic integrated circuits. These analysis processes may include curvilinear design validation and the associated flow implementations.Type: ApplicationFiled: April 22, 2015Publication date: February 25, 2016Inventors: Ruping Cao, John G. Ferguson, John D. Cayo, Alexandre Arriordaz
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Patent number: 8572533Abstract: Waiver regions may be identified by waiver identification items. The waiver identification items may be determined based on conducting a density check process. Additionally or alternatively, reference patterns for pattern matching, cell names or markers may serve as the waiver identification items. Waiver geometric items may be created for the waiver regions and added to the layout design. Based on an overlap of a density check window with the waiver geometric items and waiving threshold information, a density violation in that density check window is determined to be reported as a density violation or a waived density violation with some implementations of the invention. With some other implementations of the invention, pattern density of a density check window may not be checked if an overlap of the density check window with the waiver geometric items is above a waiving threshold value.Type: GrantFiled: November 23, 2011Date of Patent: October 29, 2013Assignee: Mentor Graphics CorporationInventors: John G. Ferguson, Bikram Garg
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Patent number: 8555212Abstract: Techniques are disclosed for modifying an existing microdevice design to improve its manufacturability. With these techniques, a designer receives manufacturing criteria associated with data in a design. The associated design data then is identified and provided to the microdevice designer, who may choose to modify the design based upon the manufacturing criteria. In this manner, the designer can directly incorporate manufacturing criteria from the foundry in the original design of the microdevice.Type: GrantFiled: December 12, 2008Date of Patent: October 8, 2013Assignee: Mentor Graphics CorporationInventors: Joseph D Sawicki, Laurence W Grodd, John G Ferguson, Sanjay Dhar
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Publication number: 20130263074Abstract: When a designer designates one or more errors identified in layout design data as false errors, waiver geometric elements corresponding to the designated false errors are created and added to the design. The waiver geometric element may be associated with a verification rule that generated its corresponding false error. When the design is subsequently analyzed using those verification rules in another verification rule check process, the waiver geometric elements are examined, and used to mask those errors associated with a waiver geometric element that would otherwise be displayed to the designer.Type: ApplicationFiled: May 23, 2013Publication date: October 3, 2013Applicant: Mentor Graphics CorporationInventor: John G. Ferguson
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Patent number: 8516399Abstract: A collaborative environment for performing physical verification processes on integrated circuit designs. Multiple physical verification results may be stored in a “unified” results database/directory (e.g., unified at least from a user's perspective), where results from various verification processes, such as Design-Rule-Check (DRC) processes, Layout-Versus-Schematic comparison (LVS) processes, Design-For-Manufacturing (DFM) processes Optical Proximity Correction (OPC) processes, and Optical Rule Check (ORC) processes are accessible from the same style of user interface, which may be a graphical user interface. The basic abilities for design team-based interactions can be equally available to each process involved in the physical verification of an integrated circuit design.Type: GrantFiled: February 18, 2010Date of Patent: August 20, 2013Assignee: Mentor Graphics CorporationInventors: James M. Paris, William M. Hogan, John G. Ferguson
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Publication number: 20130132918Abstract: Waiver regions may be identified by waiver identification items. The waiver identification items may be determined based on conducting a density check process. Additionally or alternatively, reference patterns for pattern matching, cell names or markers may serve as the waiver identification items. Waiver geometric items may be created for the waiver regions and added to the layout design. Based on an overlap of a density check window with the waiver geometric items and waiving threshold information, a density violation in that density check window is determined to be reported as a density violation or a waived density violation with some implementations of the invention. With some other implementations of the invention, pattern density of a density check window may not be checked if an overlap of the density check window with the waiver geometric items is above a waiving threshold value.Type: ApplicationFiled: November 23, 2011Publication date: May 23, 2013Inventors: John G. Ferguson, Bikram Garg
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Patent number: 8375337Abstract: Techniques are disclosed for modifying an existing microdevice design to improve its manufacturability. With these techniques, a designer receives manufacturing criteria associated with data in a design. The associated design data then is identified and provided to the microdevice designer, who may choose to modify the design based upon the manufacturing criteria. In this manner, the designer can directly incorporate manufacturing criteria from the foundry in the original design of the microdevice.Type: GrantFiled: December 12, 2008Date of Patent: February 12, 2013Assignee: Mentor Graphics CorporationInventors: Joseph D Sawicki, Laurence W Grodd, John G Ferguson, Sanjay Dhar
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Patent number: 8302039Abstract: Described herein are methods and systems for secure exchange of information related to electronic design automation. Information deemed sensitive and otherwise worthy of protection may be secured by methods such as encryption, obfuscation and other security measures. The secured information may be provided to an electronic design automation tool for processing without revealing at least some of the secured information. For instance, rule files related to integrated circuit manufacturability may be selectively annotated to indicate portions thereof deserving of protection. An encryption tool may be used to secure the information so indicated and generate a file comprising secured information related to electronic design automation. An electronic design automation tool may then unlock and use the secured information without revealing the same.Type: GrantFiled: April 12, 2010Date of Patent: October 30, 2012Assignee: Mentor Graphics CorporationInventors: John G. Ferguson, Fedor G. Pikus, Kyohei Sakajiri, Laurence W. Grodd
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Publication number: 20120167028Abstract: When a designer designates one or more errors identified in layout design data as false errors, waiver geometric elements corresponding to the designated false errors are created and added to the design. The waiver geometric element may be associated with a verification rule that generated its corresponding false error. When the design is subsequently analyzed using those verification rules in another verification rule check process, the waiver geometric elements are examined, and used to mask those errors associated with a waiver geometric element that would otherwise be displayed to the designer. A designer may also designate a waiver region based on pattern matching, cell names or layout markers in which layout region one or more verification rules may be inapplicable. A waiver region identification item for the waiver region may be associated with a waiver geometric element and the one or more verification rules.Type: ApplicationFiled: November 23, 2011Publication date: June 28, 2012Inventors: John G. Ferguson, Jonathan J. Muirhead, Bikram Garg
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Publication number: 20120047479Abstract: Techniques for incrementally analyzing layout design data are disclose. With various implementations, a subsequent incremental analysis can be made for only portions of layout design data, using a subset of available analysis criteria, or some combination of both. For example, the analysis can be limited to errors identified in a previous analysis process, to changes in the layout design data made after a previous analysis process, to particular areas specified by a designer, or some combination thereof. Still further, the analysis process may be performed using only a subset of analysis criteria relevant to the portions of the design data being analyzed, a subset of the initial analysis criteria that the design data failed in a previous analysis process, a subset of the initial analysis criteria selected by the designer, or some combination thereof. Further, such an incremental analysis process can be initiated before a previous analysis process has completed.Type: ApplicationFiled: March 9, 2008Publication date: February 23, 2012Inventors: James M. Paris, Brian Marshall, John G. Ferguson, Anant S. Adke
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Publication number: 20110265054Abstract: When a designer designates one or more errors identified in layout design data as false errors, waiver geometric elements corresponding to the designated false errors are created and added to the design. The waiver geometric element may be associated with a verification rule that generated its corresponding false error. When the design is subsequently analyzed using those verification rules in another verification rule check process, the waiver geometric elements are examined, and used to mask those errors associated with a waiver geometric element that would otherwise be displayed to the designer.Type: ApplicationFiled: November 24, 2010Publication date: October 27, 2011Inventors: John G. Ferguson, Sandeep Koranne
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Publication number: 20110016444Abstract: A collaborative environment for performing physical verification processes on integrated circuit designs. Multiple physical verification results may be stored in a “unified” results database/directory (e.g., unified at least from a user's perspective), where results from various verification processes, such as Design-Rule-Check (DRC) processes, Layout-Versus-Schematic comparison (LVS) processes, Design-For-Manufacturing (DFM) processes Optical Proximity Correction (OPC) processes, and Optical Rule Check (ORC) processes are accessible from the same style of user interface, which may be a graphical user interface. The basic abilities for design team-based interactions can be equally available to each process involved in the physical verification of an integrated circuit design.Type: ApplicationFiled: February 18, 2010Publication date: January 20, 2011Inventors: James M. Paris, William M. Hogan, John G. Ferguson
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Publication number: 20100257496Abstract: When a designer designates one or more errors identified in layout design data as false errors, waiver geometric elements corresponding to the designated false errors are created and added to the design. The waiver geometric element may be associated with a verification rule that generated its corresponding false error. When the design is subsequently analyzed using those verification rules in another verification rule check process, the waiver geometric elements are examined, and used to mask those errors associated with a waiver geometric element that would otherwise be displayed to the designer.Type: ApplicationFiled: November 3, 2009Publication date: October 7, 2010Inventors: John G. Ferguson, Sandeep Koranne
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Publication number: 20100199107Abstract: Described herein are methods and systems for secure exchange of information related to electronic design automation. Information deemed sensitive and otherwise worthy of protection may be secured by methods such as encryption, obfuscation and other security measures. The secured information may be provided to an electronic design automation tool for processing without revealing at least some of the secured information. For instance, rule files related to integrated circuit manufacturability may be selectively annotated to indicate portions thereof deserving of protection. An encryption tool may be used to secure the information so indicated and generate a file comprising secured information related to electronic design automation. An electronic design automation tool may then unlock and use the secured information without revealing the same.Type: ApplicationFiled: April 12, 2010Publication date: August 5, 2010Inventors: John G. Ferguson, Fedor G. Pikus, Kyohei Sakajiri, Laurence W. Grodd
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Patent number: 7698664Abstract: Described herein are methods and systems for secure exchange of information related to electronic design automation. Information deemed sensitive and otherwise worthy of protection may be secured by methods such as encryption, obfuscation and other security measures. The secured information may be provided to an electronic design automation tool for processing without revealing at least some of the secured information. For instance, rule files related to integrated circuit manufacturability may be selectively annotated to indicate portions thereof deserving of protection. An encryption tool may be used to secure the information so indicated and generate a file comprising secured information related to electronic design automation. An electronic design automation tool may then unlock and use the secured information without revealing the same.Type: GrantFiled: May 21, 2007Date of Patent: April 13, 2010Inventors: John G. Ferguson, Fedor G. Pikus, Kyohei Sakajiri, Laurence W. Grodd