Patents by Inventor John G. Meyers
John G. Meyers has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240082085Abstract: An overhead arm assembly for a patient support apparatus includes a user interface device. The user interface device has a support structure for supporting a personal digital assistant and a charging port for personal digital assistant.Type: ApplicationFiled: November 16, 2023Publication date: March 14, 2024Inventors: Robert M. Zerhusen, Jonathan K. Moenter, Joshua L. Meyer, Robert D. Ross, John G. Byers, Matthew R. Knue
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Patent number: 11901274Abstract: A packaged device (110) includes a substrate (114) and one or more contacts (118) disposed on a side of the substrate (114). Structures of the packaged device (110) define at least in part a recess region (120) that extends from the side of the substrate (114) and through the substrate (114), where one or more contacts (124) of a second hardware interface are disposed in the recess region (120). The one or more contacts (118) of the first hardware interface enable connection of the packaged device (110) to a printed circuit board. The one or more contacts (124) of the second hardware interface enable connection between one or more IC dies of the packaged device (110) and another IC die (150) that is a component of the packaged device (110) or of a different packaged device.Type: GrantFiled: September 25, 2015Date of Patent: February 13, 2024Assignee: Intel CorporationInventors: Bin Liu, John G. Meyers, Florence R. Pon
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Patent number: 11817438Abstract: Embodiments include systems in packages (SiPs) and a method of forming the SiPs. A SiP includes a package substrate and a first modularized sub-package over the package substrate, where the first modularized sub-package includes a plurality of electrical components, a first mold layer, and a redistribution layer. The SiP also includes a stack of dies over the package substrate, where the first modularized sub-package is disposed between the stack of dies. The SiP further includes a plurality of interconnects coupled to the stack of dies, the first modularized sub-package, and the package substrate, wherein the redistribution layer of the first modularized sub-package couples the stack of dies to the package substrate with the plurality of interconnects. The SiP may enable the redistribution layer of the first modularized sub-package to couple the electrical components to the stacked dies and the package substrate without a solder interconnect.Type: GrantFiled: January 14, 2019Date of Patent: November 14, 2023Assignee: Intel CorporationdInventors: Hyoung Il Kim, Bilal Khalaf, Juan E. Dominguez, John G. Meyers
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Patent number: 11552051Abstract: Electronic device package technology is disclosed. An electronic device package in accordance with the present disclosure can include a substrate, a plurality of electronic components in a stacked relationship, and an encapsulant material encapsulating the electronic components. Each of the electronic components can be electrically coupled to the substrate via a wire bond connection and spaced apart from an adjacent electronic component to provide clearance for the wire bond connection. The encapsulant can be disposed between center portions of adjacent electronic components. Associated systems and methods are also disclosed.Type: GrantFiled: April 1, 2017Date of Patent: January 10, 2023Assignee: Intel CorporationInventors: Florence R. Pon, John G. Meyers
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Publication number: 20220037291Abstract: An electronic assembly includes a plurality of electronic die arranged into shingles, each shingle having a multiple offset stacked die coupled by cascading connections. Each shingle is arranged in a stack of shingles with alternate shingles having die stacked in opposite directions and offset in a zigzag manner to facilitate vertical electrical connections from a top of the electronic assembly to a bottom die of each shingle.Type: ApplicationFiled: October 15, 2021Publication date: February 3, 2022Inventors: Min-Tih Ted Lai, Florence R. Pon, Yuhong Cai, John G. Meyers
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Patent number: 11171114Abstract: An electronic assembly includes a plurality of electronic die arranged into shingles, each shingle having a multiple offset stacked die coupled by cascading connections. Each shingle is arranged in a stack of shingles with alternate shingles having die stacked in opposite directions and offset in a zigzag manner to facilitate vertical electrical connections from a top of the electronic assembly to a bottom die of each shingle.Type: GrantFiled: December 2, 2015Date of Patent: November 9, 2021Assignee: Intel CorporationInventors: Min-Tih Ted Lai, Florence R. Pon, Yuhong Cai, John G. Meyers
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Patent number: 10964682Abstract: A data storage system is described that uses wafer-level packaging. In one embodiment an apparatus includes a silicon wafer, a plurality of memory cells formed directly on the wafer, an encapsulant formed over the memory cells, a plurality of wiring connections to connect the memory cells to an external interface, a memory controller, and an external interface.Type: GrantFiled: September 30, 2016Date of Patent: March 30, 2021Assignee: Intel CorporationInventors: John G. Meyers, Leo J. Craft
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Patent number: 10910347Abstract: Techniques and mechanisms for interconnecting stacked integrated circuit (IC) dies. In an embodiment, a first end of a wire is coupled to a first IC die of a stack, where a second end of the wire is further anchored to the stack independent of the coupled first end. A package material is subsequently disposed around IC dies of the stack and a first portion of the wire that includes the first end. Two-point anchoring of the wire to the stack aids in providing mechanical support to resist movement that might otherwise displace and/or deform the wire while the package material is deposited. In another embodiment, the first portion of the wire is separated from the rest of the wire, and a redistribution layer is coupled to the first portion to enable interconnection between the first IC die and another IC die of the stack.Type: GrantFiled: July 19, 2019Date of Patent: February 2, 2021Assignee: Intel CorporationInventors: Yong She, John G. Meyers, Zhicheng Ding, Richard Patten
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Patent number: 10872832Abstract: A system in package and method of making as system in package are disclosed. The system in package has a substrate (102) with a plurality of passive devices (104) mounted thereon. A molding compound (106) envelopes the plurality of passive devices (104) to define a flat surface (116) substantially parallel to a surface of the substrate (102). A plurality of integrated circuit dies (110) is coupled successively to the flat surface (116).Type: GrantFiled: December 16, 2015Date of Patent: December 22, 2020Assignee: Intel CorporationInventors: Mao Guo, John G. Meyers, Yong She, Bin Liu, Lingyan L. Tan
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Publication number: 20200227393Abstract: Embodiments include systems in packages (SiPs) and a method of forming the SiPs. A SiP includes a package substrate and a first modularized sub-package over the package substrate, where the first modularized sub-package includes a plurality of electrical components, a first mold layer, and a redistribution layer. The SiP also includes a stack of dies over the package substrate, where the first modularized sub-package is disposed between the stack of dies. The SiP further includes a plurality of interconnects coupled to the stack of dies, the first modularized sub-package, and the package substrate, wherein the redistribution layer of the first modularized sub-package couples the stack of dies to the package substrate with the plurality of interconnects. The SiP may enable the redistribution layer of the first modularized sub-package to couple the electrical components to the stacked dies and the package substrate without a solder interconnect.Type: ApplicationFiled: January 14, 2019Publication date: July 16, 2020Inventors: Hyoung Il KIM, Bilal KHALAF, Juan E. DOMINGUEZ, John G. MEYERS
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Publication number: 20200066621Abstract: A packaged device (110) includes a substrate (114) and one or more contacts (118) disposed on a side of the substrate (114). Structures of the packaged device (110) define at least in part a recess region (120) that extends from the side of the substrate (114) and through the substrate (114), where one or more contacts (124) of a second hardware interface are disposed in the recess region (120). The one or more contacts (118) of the first hardware interface enable connection of the packaged device (110) to a printed circuit board. The one or more contacts (124) of the second hardware interface enable connection between one or more IC dies of the packaged device (110) and another IC die (150) that is a component of the packaged device (110) or of a different packaged device.Type: ApplicationFiled: September 25, 2015Publication date: February 27, 2020Inventors: Bin LIU, John G. MEYERS, Florence R. PON
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Publication number: 20200013756Abstract: Electronic device package technology is disclosed. An electronic device package in accordance with the present disclosure can include a substrate, a plurality of electronic components in a stacked relationship, and an encapsulant material encapsulating the electronic components. Each of the electronic components can be electrically coupled to the substrate via a wire bond connection and spaced apart from an adjacent electronic component to provide clearance for the wire bond connection. The encapsulant can be disposed between center portions of adjacent electronic components. Associated systems and methods are also disclosed.Type: ApplicationFiled: April 1, 2017Publication date: January 9, 2020Applicant: Intel CorporationInventors: Florence R. Pon, John G. Meyers
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Patent number: 10490516Abstract: Techniques and mechanisms to facilitate connection with one or more integrated circuit (IC) dies of a packaged device. In an embodiment, the packaged device includes a first substrate coupled to a first side of a package, and a second substrate coupled to a second side of the package opposite the first side. Circuitry, coupled via the first substrate to one or more IC dies disposed in the package, includes a circuit structure disposed at a cantilever portion of the first substrate. The cantilever portion extends past one or both of an edge of the first side and an edge of the second side. In another embodiment, a hardware interface disposed on the second substrate enables coupling of the packaged device to another device.Type: GrantFiled: January 12, 2018Date of Patent: November 26, 2019Assignee: Intel CorporationInventors: John G. Meyers, Bilal Khalaf, Sireesha Gogineni, Brian J. Long
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Publication number: 20190341372Abstract: Techniques and mechanisms for interconnecting stacked integrated circuit (IC) dies. In an embodiment, a first end of a wire is coupled to a first IC die of a stack, where a second end of the wire is further anchored to the stack independent of the coupled first end. A package material is subsequently disposed around IC dies of the stack and a first portion of the wire that includes the first end. Two-point anchoring of the wire to the stack aids in providing mechanical support to resist movement that might otherwise displace and/or deform the wire while the package material is deposited. In another embodiment, the first portion of the wire is separated from the rest of the wire, and a redistribution layer is coupled to the first portion to enable interconnection between the first IC die and another IC die of the stack.Type: ApplicationFiled: July 19, 2019Publication date: November 7, 2019Inventors: Yong She, John G. Meyers, Zhicheng Ding, Richard Patten
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Publication number: 20190326249Abstract: An apparatus is provided which comprises: a plurality of circuit regions in an integrated circuit die, wherein the circuit regions comprise circuit components formed in semiconductor material, a plurality of interconnect regions to route power to the circuit regions from a surface of the integrated circuit die, wherein the interconnect regions comprise conductive traces within dielectric material and a plurality of wirebond pads on the surface of the integrated circuit die, wherein the wirebond pads comprise a substantially even distribution over the surface of the integrated circuit die. Other embodiments are also disclosed and claimed.Type: ApplicationFiled: December 29, 2016Publication date: October 24, 2019Applicant: Intel CorporationInventors: John G. Meyers, Florence R. Pon
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Patent number: 10396055Abstract: Techniques and mechanisms for interconnecting stacked integrated circuit (IC) dies. In an embodiment, a first end of a wire is coupled to a first IC die of a stack, where a second end of the wire is further anchored to the stack independent of the coupled first end. A package material is subsequently disposed around IC dies of the stack and a first portion of the wire that includes the first end. Two-point anchoring of the wire to the stack aids in providing mechanical support to resist movement that might otherwise displace and/or deform the wire while the package material is deposited. In another embodiment, the first portion of the wire is separated from the rest of the wire, and a redistribution layer is coupled to the first portion to enable interconnection between the first IC die and another IC die of the stack.Type: GrantFiled: September 25, 2015Date of Patent: August 27, 2019Assignee: Intel CorporationInventors: Yong She, John G. Meyers, Zhicheng Ding, Richard Patten
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Publication number: 20190172820Abstract: A data storage system is described that uses wafer-level packaging. In one embodiment an apparatus includes a silicon wafer, a plurality of memory cells formed directly on the wafer, an encapsulant formed over the memory cells, a plurality of wiring connections to connect the memory cells to an external interface, a memory controller, and an external interface.Type: ApplicationFiled: September 30, 2016Publication date: June 6, 2019Inventors: John G. MEYERS, Leo J. CRAFT
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Publication number: 20190019777Abstract: Techniques and mechanisms for interconnecting stacked integrated circuit (IC) dies. In an embodiment, a first end of a wire is coupled to a first IC die of a stack, where a second end of the wire is further anchored to the stack independent of the coupled first end. A package material is subsequently disposed around IC dies of the stack and a first portion of the wire that includes the first end. Two-point anchoring of the wire to the stack aids in providing mechanical support to resist movement that might otherwise displace and/or deform the wire while the package material is deposited. In another embodiment, the first portion of the wire is separated from the rest of the wire, and a redistribution Layer is coupled to the first portion to enable interconnection between the first IC die and another IC die of the stack.Type: ApplicationFiled: September 25, 2015Publication date: January 17, 2019Inventors: Yong SHE, John G. MEYERS, Zhicheng DING, Richard PATTEN
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Publication number: 20190006331Abstract: An electronics package device having a through-substrate-via comprises a substrate having a cavity and at least one electronic component (e.g., stack of dies) supported in the cavity. The electronics package device comprises a through-substrate-via disposed through the substrate and that has a pitch-to-height ratio of less than 1.5 and a pitch value that is independent of a thickness value of the substrate. Thus, the pitch of the through-substrate-via is uniform or consistent along the length of the through-substrate-via regardless of the height of the substrate. A supplemental electronics package device can be stacked on the first package device and electrically coupled to an assembly circuit board by the through-substrate-vias. A method is provided of making the electronics package device that minimizes space required for vertical interconnects for PoP devices having the electronic package device.Type: ApplicationFiled: June 30, 2017Publication date: January 3, 2019Applicant: Intel CorporationInventors: Bilal Khalaf, John G. Meyers
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Publication number: 20180366441Abstract: An electronic assembly includes a plurality of electronic die arranged into shingles, each shingle having a multiple offset stacked die coupled by cascading connections. Each shingle is arranged in a stack of shingles with alternate shingles having die stacked in opposite directions and offset in a zigzag manner to facilitate vertical electrical connections from a top of the electronic assembly to a bottom die of each shingle.Type: ApplicationFiled: December 2, 2015Publication date: December 20, 2018Inventors: Min-Tih Ted Lai, Florence R. Pon, Yuhong Cai, John G. Meyers