Patents by Inventor John Gabric
John Gabric has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8520458Abstract: A phase change memory (PCM) cycle timer and associated method are disclosed. A system includes at least one reference phase change element (PCE). The system also includes a circuit that performs a write operation on the at least one reference PCE and substantially immediately thereafter continuously senses and returns a value of a resistance of the at least one reference PCE throughout a settling time of the at least one reference PCE.Type: GrantFiled: June 22, 2012Date of Patent: August 27, 2013Assignee: International Business Machines CorporationInventors: John A. Gabric, Mark C. Lamorey, Thomas M. Maffitt
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Publication number: 20120266115Abstract: A phase change memory (PCM) cycle timer and associated method are disclosed. A system includes at least one reference phase change element (PCE). The system also includes a circuit that performs a write operation on the at least one reference PCE and substantially immediately thereafter continuously senses and returns a value of a resistance of the at least one reference PCE throughout a settling time of the at least one reference PCE.Type: ApplicationFiled: June 22, 2012Publication date: October 18, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: John A. GABRIC, Mark C. LAMOREY, Thomas M. MAFFITT
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Patent number: 8233345Abstract: A phase change memory (PCM) cycle timer and associated method are disclosed. A system includes at least one reference phase change element (PCE). The system also includes a circuit that performs a write operation on the at least one reference PCE and substantially immediately thereafter continuously senses and returns a value of a resistance of the at least one reference PCE throughout a settling time of the at least one reference PCE.Type: GrantFiled: September 8, 2010Date of Patent: July 31, 2012Assignee: International Business Machines CorporationInventors: John A Gabric, Mark C. Lamorey, Thomas M. Maffitt
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Publication number: 20120057401Abstract: A phase change memory (PCM) cycle timer and associated method are disclosed. A system includes at least one reference phase change element (PCE). The system also includes a circuit that performs a write operation on the at least one reference PCE and substantially immediately thereafter continuously senses and returns a value of a resistance of the at least one reference PCE throughout a settling time of the at least one reference PCE.Type: ApplicationFiled: September 8, 2010Publication date: March 8, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: John A. GABRIC, Mark C. LAMOREY, Thomas M. MAFFITT
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Patent number: 7613047Abstract: The embodiments of the invention provide an apparatus, method, etc. for an efficient circuit and method to measure resistance. A sense line driver for an integrated circuit memory is provided, including a sense node that receives an experiment signal from an experiment structure. An output device is connected to the sense node, wherein the output device amplifies the experiment signal. Further, a voltage divider is connected to the sense node, wherein the voltage divider includes a first device and a second device. A sensing range is controlled by an operating width/resistance range and/or an adjust signal of the second device. The adjust signal changes a gate to source voltage of the second device and holds a constant voltage over multiple sensing instances. The sensing range is different for each of the sensing instances due to a change in the operating width of the second device.Type: GrantFiled: October 5, 2006Date of Patent: November 3, 2009Assignee: International Business Machines CorporationInventors: Jonathan R. Fales, John A. Gabric, Muthukumarasamy Karthikeyan, Jeffery H. Oppold
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Publication number: 20080084760Abstract: The embodiments of the invention provide an apparatus, method, etc. for an efficient circuit and method to measure resistance. A sense line driver for an integrated circuit memory is provided, including a sense node that receives an experiment signal from an experiment structure. An output device is connected to the sense node, wherein the output device amplifies the experiment signal. Further, a voltage divider is connected to the sense node, wherein the voltage divider includes a first device and a second device. A sensing range is controlled by an operating width/resistance range and/or an adjust signal of the second device. The adjust signal changes a gate to source voltage of the second device and holds a constant voltage over multiple sensing instances. The sensing range is different for each of the sensing instances due to a change in the operating width of the second device.Type: ApplicationFiled: October 5, 2006Publication date: April 10, 2008Inventors: Jonathan R. Fales, John A. Gabric, Muthukumarasamy Karthikeyan, Jeffery H. Oppold
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Patent number: 7016251Abstract: A method for initializing a static random access memory (SRAM) device during power-up includes clamping one of a pair of bitlines of the SRAM device to a logic low potential while allowing the other of the pair of bitlines to be coupled to a charging logic high potential. An SRAM storage cell within the SRAM device is forced to a stable state by selectively allowing a wordline potential of a wordline associated with the SRAM storage cell to follow the charging logic high potential, thereby coupling the SRAM storage cell to the pair of bitlines.Type: GrantFiled: July 29, 2004Date of Patent: March 21, 2006Assignee: International Business Machines CorporationInventors: John A. Gabric, Harold Pilo
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Publication number: 20060023521Abstract: A method for initializing a static random access memory (SRAM) device during power-up includes clamping one of a pair of bitlines of the SRAM device to a logic low potential while allowing the other of the pair of bitlines to be coupled to a charging logic high potential. An SRAM storage cell within the SRAM device is forced to a stable state by selectively allowing a wordline potential of a wordline associated with the SRAM storage cell to follow the charging logic high potential, thereby coupling the SRAM storage cell to the pair of bitlines.Type: ApplicationFiled: July 29, 2004Publication date: February 2, 2006Applicant: International Business Machines CorporationInventors: John Gabric, Harold Pilo
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Publication number: 20050009312Abstract: An electronic device including: a semiconductor substrate having an array of gate conductors, each having a length and a width, comprised of dummy gate conductors and functional gate conductors extending in a widthwise direction, the gate conductors positioned substantially parallel to each other in the widthwise direction and periodically spaced apart a fixed distance in a direction substantially perpendicular to the widthwise direction.Type: ApplicationFiled: June 26, 2003Publication date: January 13, 2005Applicants: INTERNATIONAL BUSINESS MACHINES CORPORATION, INFINEON NORTH AMERICA CORPInventors: Shahid Butt, Wayne Ellis, John Gabric
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Patent number: 6177833Abstract: An integrated semiconductor module of reduced impedance and method utilizing a given chip architecture of the type having a memory circuit and a plurality of off-chip drivers and their I/O pads, the module being constructed in a configuration for operation of said memory circuit with less than the number of available drivers such that there are a number of excess drivers and output pads not used for driver operations, and one or more of these excess drivers and their pads are connected to the power terminals of the chip to provide one or more power paths through these drivers and their associated pads in parallel with the power paths of the operational drivers, and the method includes connecting the excess drivers and their output pads to the power terminals of the chip during its fabrication in a manner to provide additional power paths.Type: GrantFiled: April 30, 1999Date of Patent: January 23, 2001Assignee: International Business Machine Corp.Inventors: John A. Gabric, Michael A. Roberge, Endre P. Thoma
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Patent number: 5019772Abstract: A test selection system is provided which includes a semiconductor substrate having a pin connected thereto and an integrated circuit disposed on the substrate and connected to the pin having an operating voltage within a given voltage range. A latch conditioning circuit having an input responsive to a voltage of a given magnitude has an output connected to a latch, and a voltage control circuit operable at a voltage without the given voltage range selectively applies a control voltage of the given magnitude to the input of the latch conditioning circuit. A voltage without the given voltage range is applied to the pin during a first interval of time to produce the control voltage for establishing a test mode and a voltage within the given voltage range is applied to the pin during a second interval of time to establish a normal operating mode for the integrated circuit.Type: GrantFiled: May 23, 1989Date of Patent: May 28, 1991Assignee: International Business Machines CorporationInventors: Jeffrey H. Dreibelbis, John A. Gabric, Erik L. Hedberg
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Patent number: 4599520Abstract: An FET double boosted clock driver for producing a clock signal having an amplitude greater than the drain supply voltage. The clock output of a second clock driver is capacitively coupled to the clock output of a first clock driver. The second clock driver boosts the voltage on the source of an enhancement mode (output) FET of the first clock driver. The output FET has its gate connected to a bootstrapped node and its drain connected to a drain voltage source (VDD). A depletion mode FET forms a feedback path between the source of the output node FET and the bootstrapped node. When the bootstrapped node is bootstrapped to VDD+VT, the output FET precharges the clock output to VDD. When the potential of the clock output approaches VDD, the depletion mode FET discharges the bootstrapped node to an input clock.Type: GrantFiled: January 31, 1984Date of Patent: July 8, 1986Assignee: International Business Machines CorporationInventors: John A. Gabric, Edward F. O'Neil