Patents by Inventor John Golz

John Golz has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20060039226
    Abstract: A memory system includes a memory array, a plurality of wordline drivers, a row address decoder block which has a plurality of outputs connected to selected ones of the wordline drivers, a row selector block which has a selector lines connected to individual ones of the wordline drivers. A power management circuit having a power down input for a power down input signal (WLPWRDN) and a wordline power down output (WLPDN) is connected to the wordline drivers to lower the power consumption thereof as a function of the power down input signal.
    Type: Application
    Filed: August 17, 2005
    Publication date: February 23, 2006
    Inventors: David Hanson, Gregory Fredeman, John Golz, Hoki Kim, Paul Parries
  • Patent number: 6954387
    Abstract: In a DRAM, which includes a plurality of memory banks, there is a pair of separate flag bit registers for each bank with the flag bit registers that are shifted up/down respectively. A comparator for each bank provides a comparator output. An arbiter for each bank is connected to receive a flag bit up signal and a flag bit down signal from the flag bit registers for that bank and the comparator output from the comparator for that bank. The arbiters are connected to receive a conflict in signal and to provide a conflict out signal. The pair of flag bit registers represent a refresh status of each bank and designate memory banks or arrays that are ready for a refresh operation.
    Type: Grant
    Filed: July 15, 2003
    Date of Patent: October 11, 2005
    Assignee: International Business Machines Corporation
    Inventors: Hoki Kim, Toshiaki Kirihata, David R. Hanson, Gregory J. Fredeman, John Golz
  • Publication number: 20050013185
    Abstract: In a DRAM, which includes a plurality of memory banks, there is a pair of separate flag bit registers for each bank with the flag bit registers that are shifted up/down respectively. A comparator for each bank provides a comparator output. An arbiter for each bank is connected to receive a flag bit up signal and a flag bit down signal from the flag bit registers for that bank and the comparator output from the comparator for that bank. The arbiters are connected to receive a conflict in signal and to provide a conflict out signal. The pair of flag bit registers represent a refresh status of each bank and designate memory banks or arrays that are ready for a refresh operation.
    Type: Application
    Filed: July 15, 2003
    Publication date: January 20, 2005
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Hoki Kim, Toshiaki Kirihata, David Hanson, Gregory Fredeman, John Golz
  • Patent number: 6440638
    Abstract: A method for planarizing a layer of photoresist on a substrate. The layer of photoresist is exposed to wavelengths of radiation that the photoresist is sensitive to. The radiation is directed at the layer of photoresist at an oblique angle with respect to a major dimension of the layer of photoresist. The photoresist is developed.
    Type: Grant
    Filed: September 28, 1998
    Date of Patent: August 27, 2002
    Assignee: International Business Machines Corp.
    Inventors: John Golz, Chorng-Lii Hwang, John Zhu
  • Patent number: 6429067
    Abstract: A method for fabricating a dual gate structure, comprising providing a semiconductor substrate having a first device area and a second device area covered by a gate oxide layer and a polysilicon layer, forming a first hard mask over the polysilicon layer, said first hard mask being a material that is resistant to a first etching, but susceptible to a second etching forming a second hard mask over the first hard mask and the polysilicon layer, said second hard mask being a material that is resistant to a second etching, but susceptible to a first etching, patterning and etching said second hard mask with a first etch to form a gate pattern on a first device area, and patterning and etching said first hard mask with a second etch to transfer gate patterns on the first and second device areas.
    Type: Grant
    Filed: January 17, 2001
    Date of Patent: August 6, 2002
    Assignee: International Business Machines Corporation
    Inventors: Joyce C. Liu, James C. Brighten, Jeffrey J. Brown, John Golz, George A. Kaplita, Rebecca Mih, Senthil Srinivasan, Jin Jwang Wu, Teresa J. Wu, Chienfan Yu
  • Publication number: 20020094637
    Abstract: A method for fabricating a dual gate structure, comprising providing a semiconductor substrate having a first device area and a second device area covered by a gate oxide layer and a polysilicon layer, forming a first hard mask over the polysilicon layer, said first hard mask being a material that is resistant to a first etching, but susceptible to a second etching forming a second hard mask over the first hard mask and the polysilicon layer, said second hard mask being a material that is resistant to a second etching, but susceptible to a first etching, patterning and etching said second hard mask with a first etch to form a gate pattern on a first device area, and patterning and etching said first hard mask with a second etch to transfer gate patterns on the first and second device areas.
    Type: Application
    Filed: January 17, 2001
    Publication date: July 18, 2002
    Applicant: International Business Machines Corporation
    Inventors: Joyce C. Liu, James C. Brighten, Jeffrey J. Brown, John Golz, George A. Kaplita, Rebecca Mih, Senthil Srinivasan, Jin Jwang Wu, Teresa J. Wu, Chienfan Yu
  • Publication number: 20010006761
    Abstract: A method for planarizing a layer of photoresist on a substrate. The layer of photoresist is exposed to wavelengths of radiation that the photoresist is sensitive to. The radiation is directed at the layer of photoresist at an oblique angle with respect to a major dimension of the layer of photoresist. The photoresist is developed.
    Type: Application
    Filed: September 28, 1998
    Publication date: July 5, 2001
    Inventors: JOHN GOLZ, CHORNG-LII HWANG, JOHN ZHU