Abstract: A buffer controller includes a first write pointer generation module for generating a first write pointer that points to a first sequence of write locations in a buffer memory, that directs an input module to store a sequence of samples of a real-time signal in a buffer memory. A read pointer generation module generates a plurality of read pointers for a corresponding plurality of output modules, wherein each of the plurality of read pointers points to a sequence of read locations in the buffer memory, in a buffer order, that contain the sequence of samples.

Abstract: A real time clock module maintains operating and timing parameters in “non-volatile” or persistent memory when an integrated circuit is powered down. The real time clock module provides is divided into an analog and a digital domain. The analog domain contains a number of persistent registers to store operational parameters and timing parameters. These persistent registers are powered by a battery and receive a timing clock signal from a crystal oscillator. A clock domain-crossing module operably couples to the persistent registers and allows the analog domain and the digital domain to be synchronized. An input buffer receives the operational and timing parameters for the persistent registers from the digital domain and an output buffer allows the digital domain to retrieve the operational parameters and timing parameters from the persistent registers according to the clock crossing domain module.

Abstract: A real time clock module maintains operating and timing parameters in “non-volatile” or persistent memory when an integrated circuit is powered down. The real time clock module provides is divided into an analog and a digital domain. The analog domain contains a number of persistent registers to store operational parameters and timing parameters. These persistent registers are powered by a battery and receive a timing clock signal from a crystal oscillator. A clock domain-crossing module operably couples to the persistent registers and allows the analog domain and the digital domain to be synchronized. An input buffer receives the operational and timing parameters for the persistent registers from the digital domain and an output buffer allows the digital domain to retrieve the operational parameters and timing parameters from the persistent registers according to the clock crossing domain module.