Abstract: An apparatus for link layer port-based hardware implemented acceptance rate limiting control is presented. The apparatus employs a single up-down counter tracking a receive port buffer occupancy level. The single up-down counter is incremented by a receive line rate clock signal time truncated by a frame receive signal and a feedback frame acceptance control signal. The single up-down counter is decremented at an Service Level Agreement (SLA) agreed upon committed rate at which content is extracted from the receive port buffer. Outputs of comparators determining when the port receive buffer occupancy level is below a low watermark receive port buffer occupancy level, and when the receive port buffer occupancy level is above a maximum burst size, are provided to a master slave flip flop generating the frame acceptance control signal exhibiting hysteresis as the port receive buffer occupancy level transitions between the low watermark and the maximum burst size receive port buffer occupancy levels.

Abstract: Techniques for determining and verifying connectivity in an electronic device from a representation of the electronic device are disclosed. Connectivity is determined by identifying electronic components and signals in the electronic device and providing an indication of the identified electronic components and signals. Based on identified components and signals, a determination is made as to whether the electronic device satisfies one or more criteria, to thereby verify connectivity. In some embodiments, the indication provided after connectivity has been determined is subsequently used in verifying connectivity.

Abstract: Electronic device modelling methods and systems are provided. A model of an electronic device is generated by identifying electronic components in the electronic device, searching component models to locate a component model for each electronic component, and recording each component model in a device model for the electronic device. A previously generated device model may subsequently be accessed and updated in a data store. Electronic device structure analysis techniques are also disclosed. Electronic components and any sub-components thereof are identified from a representation of an electronic device, and an indication of any identified components and sub-components is provided. The indication may then be used in generating a model of the electronic device for functional simulation, further structural analysis, or other purposes.

Abstract: A system for implementing time stamp related features in a real time stamp distribution system is discussed. The distribution system derives a real time stamp (RTS) at a master timekeeping network element and distributes the RTS to associated network elements by way of a number of distribution techniques. Under certain network conditions, the real time stamp may not reach one or more of the network elements at the valid real time. In the present system, the network elements are able to derive a local time based on timing information recorded at the network element. Thus the system can detect an error in the time stamp delivered to a network element and can correct the time stamp utilizing a local time stamp feature.

Abstract: An apparatus for link layer port-based hardware implemented acceptance rate limiting control is presented. The apparatus employs a single up-down counter tracking a receive port buffer occupancy level. The single up-down counter is incremented by a receive line rate clock signal time truncated by a frame receive signal and a feedback frame acceptance control signal. The single up-down counter is decremented at an Service Level Agreement (SLA) agreed upon committed rate at which content is extracted from the receive port buffer. Outputs of comparators determining when the port receive buffer occupancy level is below a low watermark receive port buffer occupancy level, and when the receive port buffer occupancy level is above a maximum burst size, are provided to a master slave flip flop generating the frame acceptance control signal exhibiting hysteresis as the port receive buffer occupancy level transitions between the low watermark and the maximum burst size receive port buffer occupancy levels.