Abstract: Systems, apparatuses, and methods disclosed herein may be directed to clips for medical implementation, including clips for a portion of a heart. The clips may be configured to close the portion of the heart, to reduce blood flow therethrough as well as passage of clots or other undesired materials. In examples, the clips may be configured to close the left atrial appendage (LAA). The closure of the LAA may reduce the possibility of stroke or other maladies stemming from fluid flow with the LAA. In examples, the clips may be positioned exterior of the LAA, to extend over an outer surface of the LAA for closure.

Abstract: Systems and methods for balancing a pair of battery cells are described. A controller can determine a voltage difference based on a first voltage of a first battery cell and a second voltage of a second battery cell. The controller can determine a current difference between current of an inductor and a current limit of the inductor, where the inductor can be connected to a node between the first and second battery cells. The controller can identify at least one switching elements among a plurality of switching elements based on the voltage difference and the current difference. The controller can activate the identified switching elements to perform battery cell balancing between the first battery cell and the second battery cell.

Abstract: According to certain aspects, the present embodiments are related to systems and methods providing an autonomous adapter pass through mode in a battery charger. For example, when an adapter is connected to the battery charger, but the system is idling, embodiments allow for power from the adapter to be directly coupled to the battery charger output, and main switching to be stopped, thereby dramatically reducing battery charger current consumption. These and other embodiments provide various circuitry and techniques to ensure that the battery is protected in this mode. According to further aspects, the present embodiments provide for the charger itself to autonomously enter and exit the adapter pass through mode, thereby eliminating the need for excessive processing overhead in components external to the battery charger.

Abstract: A power loss protection integrated circuit includes a storage capacitor terminal (STR), an autonomous capacitor health check circuit, and a capacitor fault terminal (CF). The capacitor health check circuit autonomously performs periodic capacitor check operations. In a check operation, current is sinked from the STR terminal for a predetermined time and in a predetermined way. If during this time the voltage on the STR terminal STR drops below a predetermined voltage, then a digital signal CF is asserted onto the CF terminal. Immediately following each capacitor check, a charging voltage is driven onto the STR terminal to recharge the external capacitors coupled to the STR terminal. In one example, the integrated circuit further includes a current switch circuit (eFuse) and a buck/boost controller. The capacitor health check circuit is only enabled during normal mode operation of the integrated circuit, and the check circuit disables boost operation during capacitor checks.

Abstract: According to certain aspects, the present embodiments are related to systems and methods providing an autonomous adapter pass through mode in a battery charger. For example, when an adapter is connected to the battery charger, but the system is idling, embodiments allow for power from the adapter to be directly coupled to the battery charger output, and main switching to be stopped, thereby dramatically reducing battery charger current consumption. These and other embodiments provide various circuitry and techniques to ensure that the battery is protected in this mode. According to further aspects, the present embodiments provide for the charger itself to autonomously enter and exit the adapter pass through mode, thereby eliminating the need for excessive processing overhead in components external to the battery charger.

Abstract: A power loss protection integrated circuit includes a storage capacitor terminal (STR), an autonomous capacitor health check circuit, and a capacitor fault terminal (CF). The capacitor health check circuit autonomously performs periodic capacitor check operations. In a check operation, current is sinked from the STR terminal for a predetermined time and in a predetermined way. If during this time the voltage on the STR terminal STR drops below a predetermined voltage, then a digital signal CF is asserted onto the CF terminal. Immediately following each capacitor check, a charging voltage is driven onto the STR terminal to recharge the external capacitors coupled to the STR terminal. In one example, the integrated circuit further includes a current switch circuit (eFuse) and a buck/boost controller. The capacitor health check circuit is only enabled during normal mode operation of the integrated circuit, and the check circuit disables boost operation during capacitor checks.

Abstract: A power loss protection integrated circuit includes a storage capacitor terminal (STR), an autonomous capacitor health check circuit, and a capacitor fault terminal (CF). The capacitor health check circuit autonomously performs periodic capacitor check operations. In a check operation, current is sinked from the STR terminal for a predetermined time and in a predetermined way. If during this time the voltage on the STR terminal STR drops below a predetermined voltage, then a digital signal CF is asserted onto the CF terminal. Immediately following each capacitor check, a charging voltage is driven onto the STR terminal to recharge the external capacitors coupled to the STR terminal. In one example, the integrated circuit further includes a current switch circuit (eFuse) and a buck/boost controller. The capacitor health check circuit is only enabled during normal mode operation of the integrated circuit, and the check circuit disables boost operation during capacitor checks.

Abstract: A power loss protection integrated circuit includes a current switch circuit (eFuse), a VIN terminal, a VOUT terminal, a buck/boost controller, and a storage capacitor terminal STR. The controller is adapted to work: 1) as a boost to take a low voltage from the VOUT terminal and to output a larger charging voltage onto the STR terminal, or 2) as a buck to take a higher voltage from the STR terminal and to buck it down to a lower voltage required on the VOUT terminal. The current switch circuit outputs a digital undervoltage signal (UV) and a digital high current signal (HC). These signals are communicated on-chip to the controller. Asserting UV causes the converter to begin operating in the buck mode. Asserting HC prevents the converter from operating in the boost mode.

Abstract: An adaptive USB port controller is disclosed. In an exemplary embodiment, a system comprises a source, a power adapter, a USB port controller, a USB plug and cable, and a device. In one example, the device includes a rechargeable battery. After connecting the device to the USB port controller via the USB plug and cable, a reconfigurable module within the USB port controller sets a power mode by: (1) configuring an impedance network to present impedance modes that indicate available power modes, (2) detecting voltages on one or more of the USB conductors in response to each impedance mode, and (3) comparing the detected voltages to reference voltage levels to set one of multiple power modes. The reconfigurable module then controls the power adapter to transfer power according to the determined power mode.

Abstract: A power loss protection integrated circuit includes a current switch circuit portion (eFuse) and an autonomous limit checking circuit. The limit checking circuit includes an input analog multiplexer, an ADC, a plurality of capture registers, a state machine, and a flag output terminal. For each capture register, the limit checking circuit further includes an associated lower limit register and an associated upper limit register. The state machine controls the multiplexer and the capture registers so the ADC digitizes voltages on various nodes to the monitored, and stores the results into corresponding capture registers. In integrated circuit has circuitry that allows both a high voltage as well as a high current to be monitored. The value in a capture register is compared to upper and lower limit values. If any capture value is determined to be outside the limits, then a digital flag signal is asserted onto the flag output terminal.

Abstract: A power loss protection integrated circuit includes a current switch circuit portion (eFuse) and an autonomous limit checking circuit. The limit checking circuit includes an input analog multiplexer, an ADC, a plurality of capture registers, a state machine, and a flag output terminal. For each capture register, the limit checking circuit further includes an associated lower limit register and an associated upper limit register. The state machine controls the multiplexer and the capture registers so the ADC digitizes voltages on various nodes to the monitored, and stores the results into corresponding capture registers. In integrated circuit has circuitry that allows both a high voltage as well as a high current to be monitored. The value in a capture register is compared to upper and lower limit values. If any capture value is determined to be outside the limits, then a digital flag signal is asserted onto the flag output terminal.

Abstract: A power loss protection integrated circuit includes a current switch circuit (eFuse), a VIN terminal, a VOUT terminal, a buck/boost controller, and a storage capacitor terminal STR. The controller is adapted to work: 1) as a boost to take a low voltage from the VOUT terminal and to output a larger charging voltage onto the STR terminal, or 2) as a buck to take a higher voltage from the STR terminal and to buck it down to a lower voltage required on the VOUT terminal. The current switch circuit outputs a digital undervoltage signal (UV) and a digital high current signal (HC). These signals are communicated on-chip to the controller. Asserting UV causes the converter to begin operating in the buck mode. Asserting HC prevents the converter from operating in the boost mode.

Abstract: An adaptive USB port controller is disclosed. In an exemplary embodiment, a system comprises a source, a power adapter, a USB port controller, a USB plug and cable, and a device. In one example, the device includes a rechargeable battery. After connecting the device to the USB port controller via the USB plug and cable, a reconfigurable module within the USB port controller sets a power mode by: (1) configuring an impedance network to present impedance modes that indicate available power modes, (2) detecting voltages on one or more of the USB conductors in response to each impedance mode, and (3) comparing the detected voltages to reference voltage levels to set one of multiple power modes. The reconfigurable module then controls the power adapter to transfer power according to the determined power mode.

Abstract: A multi-state battery charger includes a single-stage AC-to-DC switching converter, where the single-stage converter receives an AC supply voltage and directly charges a rechargeable battery without there being any intervening second power stage. A novel battery charger controller integrated circuit in the converter's secondary side detects profile selection resistor values, monitors battery voltage, monitors charging current, monitors battery temperature, controls a protection transistor, and sends a control signal back to a PWM in the primary side. The controller includes a flexible preprogrammed digital state machine circuit that is configured to control the converter from charging state to charging state so that the battery is charged in accordance with a selected one of multiple preprogrammed different multi-state battery charging profiles, where at least one of the profiles has at least one CC (constant current) state and one CV (constant voltage) state.

Abstract: A multi-state battery charger includes a single-stage AC-to-DC switching converter, where the single-stage converter receives an AC supply voltage and directly charges a rechargeable battery without there being any intervening second power stage. A novel battery charger controller integrated circuit in the converter's secondary side detects profile selection resistor values, monitors battery voltage, monitors charging current, monitors battery temperature, controls a protection transistor, and sends a control signal back to a PWM in the primary side. The controller includes a flexible preprogrammed digital state machine circuit that is configured to control the converter from charging state to charging state so that the battery is charged in accordance with a selected one of multiple preprogrammed different multi-state battery charging profiles, where at least one of the profiles has at least one CC (constant current) state and one CV (constant voltage) state.

Abstract: Systems and methods for cell anomaly detection are provided. The disclosed systems and methods of cell anomaly detection may use a single circuit to detect both cell-open and imbalance conditions. Disclosed embodiments may incorporate a continuous or a sampled time system (i.e. cell anomaly detection is performed when an enable signal is active). An example embodiment includes receiving voltages of a plurality of cells of a battery pack; converting the received voltages to currents; determining a maximum current of the currents; determining whether at least one of the currents is anomalous; and reporting the at least one anomalous current as indicative of a bad cell.

Abstract: One embodiment includes a power system. The system includes a power switch device that is activated to provide an output voltage to a load in response to an input voltage. The power switch device includes a control terminal and a bulk connection. The system also includes a reverse voltage control circuit configured to passively couple the input voltage to one of the control terminal and the bulk connection in response to a reverse voltage condition in which an amplitude of the input voltage becomes negative. The system further includes an output shutoff circuit configured to passively couple the output voltage to a neutral-voltage rail during the reverse voltage condition.

Abstract: One embodiment includes a power system. The system includes a power switch device that is activated to provide an output voltage to a load in response to an input voltage. The power switch device includes a control terminal and a bulk connection. The system also includes a reverse voltage control circuit configured to passively couple the input voltage to one of the control terminal and the bulk connection in response to a reverse voltage condition in which an amplitude of the input voltage becomes negative. The system further includes an output shutoff circuit configured to passively couple the output voltage to a neutral-voltage rail during the reverse voltage condition.

Abstract: With batteries or cells, particularly lithium ion cells, it is important to determine when one or more cells have entered a fault condition (i.e., overvoltage or undervoltage). Conventional circuits employ measuring circuits that use multiple bandgap circuits and high voltage components. These conventional circuits, however, consume a great deal of area because of the use of these multiple bandgap circuits and the high voltage components. Here, a circuit is provided that reduces the number of bandgap circuits and reduces the number of high voltage components, reducing the area consumed and reducing the overall cost of production compared to conventional circuits.

Abstract: Systems and methods for determining a state of charge (SOC) of an electrical energy storage device are disclosed. In one embodiment, a system is provided for determining the SOC of an electrical energy storage device comprises at least one memristor coupled in series with the electrical energy storage device to monitor charge current and discharge current of the electrical energy storage device. The system also includes a readout controller configured to determine the SOC of the electrical energy storage device based on the resistance of the memristor.