Abstract: An apparatus that moves stimulus data and response data between a memory and a device under test (DUT) over a plurality of data transfer banks. In a first mode the data transfer banks output the stimulus data to the DUT as respective independent banks of serial stimulus data channels, and write the response data into the memory responsive to data provided as respective independent banks of channels of serial data from the DUT. In a second mode the data transfer banks output the stimulus data to the DUT as a single bank of combined serial stimulus data channels, and write the response data into the memory responsive to the data provided as a combined single bank of channels of serial data from the DUT.

Abstract: A signal analyzer comprises: a first tuner configured to tune to a first frequency band and to output first tuner data; a memory device configured to store the first tuner data; a spectrum calculator configured to calculate a series of spectra for the first tuner data; a processor configured to determine a presence of a transmission of interest within the first tuner data based on the series of spectra; a second tuner configured to receive the first tuner data stored in the memory device and to tune to a second frequency band including the transmission of interest. The second tuner outputs second tuner data in response to the stored first tuner data. The signal analyzer also comprises a transmission start time detector configured to receive the second tuner data and to determine a start time for the transmission of interest from the second tuner data.

Abstract: An apparatus for phase alignment of clock signals includes a sampling circuit that samples a first clock signal on edges of a reference clock signal and that samples the reference clock signal on edges of the first clock signal, to generate a phase signal indicative of relative phase between the first clock signal and the reference clock signal. An alignment control circuit generates a control signal responsive to the phase signal, the control signal setting a phase shift direction for the first clock signal. A phase shifter shifts a phase of the first clock signal in the phase shift direction responsive to the control signal to align the phase of the first clock signal with a phase of the reference clock signal.

Abstract: An apparatus that moves stimulus data and response data between a memory and a device under test (DUT) over a plurality of data transfer banks. In a first mode the data transfer banks output the stimulus data to the DUT as respective independent banks of serial stimulus data channels, and write the response data into the memory responsive to data provided as respective independent banks of channels of serial data from the DUT. In a second mode the data transfer banks output the stimulus data to the DUT as a single bank of combined serial stimulus data channels, and write the response data into the memory responsive to the data provided as a combined single bank of channels of serial data from the DUT.

Abstract: A time accumulator is adjustable to provide sufficient calculation time regardless of the clock frequency. The time accumulator includes a first register storing a current time and a second register storing a time increment value corresponding to a multiplier multiplied by an original time increment associated with a clock pulse of a clock signal. The clock signal is divided into computation intervals, in which each computation interval includes a predetermined number of clock pulses equivalent to the value of the multiplier. The time accumulator further includes a summation node for adding the current time to the time value to produce an updated current time each computation interval.

Abstract: A time synchronization system synchronizes local clocks of locating units within a communication system using a known external signal. Each of the locating units receives a radio frequency (RF) signal from a transmitter at a known geographical location and measures the RF signal to produce a respective measurement of the signal and a respective timestamp of the measurement recorded at substantially the same time of the local clocks of the locating units. A controller determines a measured time difference of arrival between the locating units using the measurements and timestamps, computes a time synchronization error between the locating units from a difference between the measured time difference of arrival and an expected time difference of arrival and provides a respective time adjustment to each of the locating units to offset the time synchronization error.

Abstract: A spectrum analyzer corrects for internal frequency errors in a reference oscillator using a timing control signal. The reference oscillator provides a reference signal at a reference frequency. An error detection circuit determines an error in the reference frequency using the timing control signal and produces an error correction signal for use by a frequency conversion device in adjusting an output frequency thereof to compensate for the frequency error in the reference frequency.

Abstract: A versatile signal generator for generating digitally modulated test signals computed in real-time is provided. Each of the blocks ol the versatile signal generator, including the MUX, coder, map, filter, re-sampler, and modulator, are implemented in a sufficiently flexible manner so as to allow ready configuration to produce any of a variety of digitally modulated signals as well as high quality analog modulated signals. Each of the blocks may be implemented using ASICs and RAM that allow to obtain high symbol rates while being capable of being reconfigured for different test signals as needed. The versatile signal generator has a real time input for receiving input data to modulate the test signal in real time.

Abstract: A phase detector for symbol clock recovery in a digital communications system determines the phase error of a local symbol clock from the symbol rate of a transmitted signal by sampling the transmitted signal to obtain a first sample at a fraction of a symbol period after the symbol clock and to obtain a second sample at an equal fraction of a symbol period before the symbol clock, and determining a phase error equal to the difference between a function of the magnitude of the first sample and a function of the magnitude of the second sample. The function is preferably the square of the magnitude or the logarithm of the magnitude of the samples.

Abstract: A direct digital synthesizer of the phase-accumulator type, constructed entirely of binary-radix digital hardware, generates signals with decimally-defined frequency resolution. The synthesizer is supplied with a clock signal which is also decimally-defined. The usual decimal-binary incompatibility problems of such a combination are overcome by the use of a phase accumulator which is partitioned into two segments. The first segment is assigned the most significant portion of the desired frequency, and the other segment is assigned the remaining portion of the desired frequency. The two segments have different arithmetic moduli. Typically, the modulus of the first segment is a power of two, while that of the second segment is an integer other than a power of two. A procedure is given for determining both the point of partition and the second arithmetic modulus.