Abstract: Methods and systems to control stacked hexapod platforms for use as tools, which function with both high accuracy and high precision are provided. In some embodiments, the methods and systems include a convergence of modern control theory, and machine learning. Furthermore, some embodiments provide control algorithms to carry out autonomous in-space assembly operations using assemblers. Some embodiments provide methods and systems which combine long-reach low precision manipulators and smaller, high-precision assembler with interchangeable tools.

Abstract: A neuromodulation therapy is delivered via at least one electrode implanted subcutaneously and superficially to a fascia layer superficial to a nerve of a patient. In one example, an implantable medical device is deployed along a superficial surface of a deep fascia tissue layer superficial to a nerve of a patient. Electrical stimulation energy is delivered to the nerve through the deep fascia tissue layer via implantable medical device electrodes.

Abstract: A neuromodulation therapy is delivered via at least one electrode implanted subcutaneously and superficially to a fascia layer superficial to a nerve of a patient. In one example, an implantable medical device is deployed along a superficial surface of a deep fascia tissue layer superficial to a nerve of a patient. Electrical stimulation energy is delivered to the nerve through the deep fascia tissue layer via implantable medical device electrodes.

Abstract: A splash guard for installation about a pair of substantially horizontally extending rails of a transfer bench for cooperating with a shower curtain to prevent water from splashing out of a shower stall or bath tub while the transfer bench is positioned to extend into and out of the stall or tub for supporting an invalid or disabled person. The splash guard includes at least one substantially flat member that is slotted to define one or more rail-receiving passages that permit the splash guard to be installed on and removed from the horizontally extending rails of the transfer bench. In preferred practice, the splash guard is defined by at least two substantially flat members that, when installed on the rails of a transfer bench, extend substantially vertically, side-by-side, with most of the open-slot area of one of the flat members being closed by non-slotted portions of one or more of the other flat members to prevent water from being splashed through the rail-receiving passages.

Abstract: In a peripheral controller of a data processing system having a plurality of system units electrically coupled to a common communication bus for asynchronous intercommunication, an array of counters responsive to both hardware and firmware are connected in a manner to form a serial control data path. Prior to a data transfer, a serial data stream including an offset range count, a range count and a main memory address is shifted through the counters under firmware control. During a data transfer, the firmware enables the hardware control to increment the memory address and decrement the range count to accommodate the higher data transfer rates characteristic of hardware control.

Abstract: In a data processing system wherein a plurality of functional units are interconnected by way of a common communication bus in an environment of high data transfer rates, a logic control system is provided for interjecting firmware control during a data transfer between a disk device and main memory to accommodate unsolicited bus requests without incurring data errors or compromising the data transfer rate. Data transferred between the disk device and a disk controller interfacing directly with the common bus is routed through a FIFO (first-in-first-out) buffer under hardware control. The buffer signals the absence of data in its input register and the presence of data in its output register. The signals are logically combined and ANDed with a firmware controlled logic gate to indicate the occurrence of data transfer states. During such transfer states, data is transferred under hardware control between the FIFO buffer and main memory.

Abstract: A logic data control system including a first-in-first-out (FIFO) buffer predictor is provided for the transfer of data between a main memory unit and a peripheral control unit of a data processing system. Data from main memory is stored into the input registers of the peripheral unit, and thereafter loaded into an array of data FIFOs for transfer to a peripheral storage device. A predictor FIFO operates in parallel with the data FIFOs, and is loaded with a dummy or flag byte each time a data request is made to main memory. When a data word is loaded into the data FIFOs, the input register of the predictor FIFO is sensed. If the flag byte in the predictor FIFO has dropped from the input register into the FIFO stack, a request is issued to main memory for an additional data word. When the data FIFOs are filled, the predictor FIFO also is filled and cannot generate an additional data request until a data byte has been unloaded from the data FIFOs to a peripheral storage device.