Patents by Inventor John Harada

John Harada has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20160256736
    Abstract: A footrest device for supporting and exercising a user's feet and legs. The footrest device includes a pair of footrests that are pivotally connected to the opposed ends of a rigid elongated member, which is suspended by a non-rigid suspension member. The footrests are pivotally connected to the rigid elongated member. The footrest device can be suspended from a fixed object, such as the underside of a desk. Alternatively, the footrest device can include, and be suspended from, a mobile base that is positioned on the floor.
    Type: Application
    Filed: May 16, 2016
    Publication date: September 8, 2016
    Applicant: Active Ideas LLC
    Inventors: John Harada, John Godoy
  • Patent number: 9403049
    Abstract: A suspended footrest device for supporting and exercising a user's feet and legs. The footrest device includes a pair of footrests that are pivotally connected to the opposed ends of a rigid elongated member. A non-rigid suspension member is connected to a medial section of the elongated member to suspend the footrests. The footrests are pivotally connected to the rigid elongated member.
    Type: Grant
    Filed: July 7, 2015
    Date of Patent: August 2, 2016
    Assignee: ACTIVE IDEAS LLC
    Inventors: John Harada, John Godoy
  • Publication number: 20150306449
    Abstract: A suspended footrest device for supporting and exercising a user's feet and legs. The footrest device includes a pair of footrests that are pivotally connected to the opposed ends of a rigid elongated member. A non-rigid suspension member is connected to a medial section of the elongated member to suspend the footrests. The footrests are pivotally connected to the rigid elongated member using a ball-and-socket joint and/or a rotatable turntable joint. The suspended footrest can also optionally include a damper positioned between each footrest and the respective end of the rigid elongated member for dampening the pivotal movement of the ball-and-socket joint. Optionally, the suspended footrest device can include a rigid elongated support member that has one end rigidly connected to a leg of a chair, and the second end connected to the non-rigid suspension member, whereby the footrests and the rigid elongated member are suspended by the support member.
    Type: Application
    Filed: July 7, 2015
    Publication date: October 29, 2015
    Applicant: ACTIVE IDEAS LLC
    Inventors: John Harada, John Godoy
  • Patent number: 8390109
    Abstract: In a chip package, semiconductor dies in a vertical stack of semiconductor dies or chips (which is referred to as a ‘plank stack’) are separated by a mechanical spacer (such as a filler material or an adhesive). Moreover, the chip package includes a substrate at a right angle to the plank stack, which is electrically coupled to the semiconductor dies along an edge of the plank stack. In particular, electrical pads proximate to a surface of the substrate (which are along a stacking direction of the plank stack) are electrically coupled to pads that are proximate to edges of the semiconductor dies by an intervening conductive material, such as: solder, stud bumps, plated traces, wire bonds, spring connectors, a conductive adhesive and/or an anisotropic conducting film. Note that the chip package may facilitate high-bandwidth communication of signals between the semiconductor dies and the substrate.
    Type: Grant
    Filed: February 17, 2011
    Date of Patent: March 5, 2013
    Assignee: Oracle America, Inc.
    Inventors: Darko R. Popovic, Matthew D. Giere, Bruce M. Guenin, Theresa Y. Sze, Ivan Shubin, John A. Harada, David C. Douglas, Jing Shi
  • Patent number: 8373280
    Abstract: An assembly component and a technique for assembling a chip package using the assembly component are described. This chip package includes a set of semiconductor dies that are arranged in a stack in a vertical direction, which are offset from each other in a horizontal direction to define a stepped terraced at one side of the vertical stack. Moreover, the chip package may be assembled using the assembly component. In particular, the assembly component may include a housing having another stepped terrace. This other stepped terrace may include a sequence of steps in the vertical direction, which are offset from each other in the horizontal direction. Furthermore, the housing may be configured to mate with the set of semiconductor dies such that the set of semiconductor dies are arranged in the stack in the vertical direction. For example, the other stepped terrace may approximately be a mirror image of the stepped terrace.
    Type: Grant
    Filed: September 1, 2010
    Date of Patent: February 12, 2013
    Assignee: Oracle America, Inc.
    Inventors: John A. Harada, Robert J. Drost, David C. Douglas
  • Patent number: 8290319
    Abstract: A ramp-stack chip package is described. This chip package includes a vertical stack of semiconductor dies or chips that are offset from each other in a horizontal direction, thereby defining a stepped terrace. A high-bandwidth ramp component, which is positioned approximately parallel to the stepped terrace, is mechanically coupled to the semiconductor dies. Furthermore, the ramp component includes an optical waveguide that conveys the optical signal, and an optical coupling component that optically couples the optical signal to one of the semiconductor dies, thereby facilitating high-bandwidth communication of the optical signal between the semiconductor die and the ramp component.
    Type: Grant
    Filed: August 25, 2010
    Date of Patent: October 16, 2012
    Assignee: Oracle America, Inc.
    Inventors: John A. Harada, David C. Douglas, Robert J. Drost
  • Patent number: 8283766
    Abstract: A ramp-stack chip package is described. This chip package includes a vertical stack of semiconductor dies or chips that are offset from each other in a horizontal direction, thereby defining a terrace with exposed pads. A high-bandwidth ramp component, which is positioned approximately parallel to the terrace, is electrically and mechanically coupled to the exposed pads. For example, the ramp component may be coupled to the semiconductor dies using: solder, microsprings and/or an anisotropic conducting film. Furthermore, each of the semiconductor dies includes a static bend so that an end segment of each of the semiconductor dies is parallel to the direction and is mechanically coupled to the ramp component. These end segments may facilitate high-bandwidth communication of signals between the chips and the ramp component, for example, via proximity communication.
    Type: Grant
    Filed: September 2, 2010
    Date of Patent: October 9, 2012
    Assignee: Oracle America, Inc
    Inventors: John A. Harada, David C. Douglas, Robert J. Drost
  • Publication number: 20120211878
    Abstract: In a chip package, semiconductor dies in a vertical stack of semiconductor dies or chips (which is referred to as a ‘plank stack’) are separated by a mechanical spacer (such as a filler material or an adhesive). Moreover, the chip package includes a substrate at a right angle to the plank stack, which is electrically coupled to the semiconductor dies along an edge of the plank stack. In particular, electrical pads proximate to a surface of the substrate (which are along a stacking direction of the plank stack) are electrically coupled to pads that are proximate to edges of the semiconductor dies by an intervening conductive material, such as: solder, stud bumps, plated traces, wire bonds, spring connectors, a conductive adhesive and/or an anisotropic conducting film. Note that the chip package may facilitate high-bandwidth communication of signals between the semiconductor dies and the substrate.
    Type: Application
    Filed: February 17, 2011
    Publication date: August 23, 2012
    Applicant: ORACLE INTERNATIONAL CORPORATION
    Inventors: Darko R. Popovic, Matthew D. Giere, Bruce M. Guenin, Theresa Y. Sze, Ivan Shubin, John A. Harada, David C. Douglas, Jing Shi
  • Publication number: 20120056327
    Abstract: A ramp-stack chip package is described. This chip package includes a vertical stack of semiconductor dies or chips that are offset from each other in a horizontal direction, thereby defining a terrace with exposed pads. A high-bandwidth ramp component, which is positioned approximately parallel to the terrace, is electrically and mechanically coupled to the exposed pads. For example, the ramp component may be coupled to the semiconductor dies using: solder, microsprings and/or an anisotropic conducting film. Furthermore, each of the semiconductor dies includes a static bend so that an end segment of each of the semiconductor dies is parallel to the direction and is mechanically coupled to the ramp component. These end segments may facilitate high-bandwidth communication of signals between the chips and the ramp component, for example, via proximity communication.
    Type: Application
    Filed: September 2, 2010
    Publication date: March 8, 2012
    Applicant: ORACLE INTERNATIONAL CORPORATION
    Inventors: John A. Harada, David C. Douglas, Robert J. Drost
  • Publication number: 20120051695
    Abstract: A ramp-stack chip package is described. This chip package includes a vertical stack of semiconductor dies or chips that are offset from each other in a horizontal direction, thereby defining a stepped terrace. A high-bandwidth ramp component, which is positioned approximately parallel to the stepped terrace, is mechanically coupled to the semiconductor dies. Furthermore, the ramp component includes an optical waveguide that conveys the optical signal, and an optical coupling component that optically couples the optical signal to one of the semiconductor dies, thereby facilitating high-bandwidth communication of the optical signal between the semiconductor die and the ramp component.
    Type: Application
    Filed: August 25, 2010
    Publication date: March 1, 2012
    Applicant: ORACLE INTERNATIONAL CORPORATION
    Inventors: John A. Harada, David C. Douglas, Robert J. Drost
  • Publication number: 20120049376
    Abstract: An assembly component and a technique for assembling a chip package using the assembly component are described. This chip package includes a set of semiconductor dies that are arranged in a stack in a vertical direction, which are offset from each other in a horizontal direction to define a stepped terraced at one side of the vertical stack. Moreover, the chip package may be assembled using the assembly component. In particular, the assembly component may include a housing having another stepped terrace. This other stepped terrace may include a sequence of steps in the vertical direction, which are offset from each other in the horizontal direction. Furthermore, the housing may be configured to mate with the set of semiconductor dies such that the set of semiconductor dies are arranged in the stack in the vertical direction. For example, the other stepped terrace may approximately be a mirror image of the stepped terrace.
    Type: Application
    Filed: September 1, 2010
    Publication date: March 1, 2012
    Applicant: ORACLE INTERNATIONAL CORPORATION
    Inventors: John A. Harada, Robert J. Drost, David C. Douglas
  • Patent number: 7612253
    Abstract: The present invention is directed to plant genetic engineering. In particular, it relates to methods of modulating cytokinin related processes in a plant and selecting a plant having a phenotype associated with an altered cytokinin-related process.
    Type: Grant
    Filed: October 25, 2006
    Date of Patent: November 3, 2009
    Assignee: Regents of the University of California
    Inventors: John Harada, Sandra Stone, Julie Pelletier
  • Publication number: 20070050867
    Abstract: The present invention is directed to plant genetic engineering. In particular, it relates to methods of modulating cytokinin related processes in a plant and selecting a plant having a phenotype associated with an altered cytokinin-related process.
    Type: Application
    Filed: October 25, 2006
    Publication date: March 1, 2007
    Applicant: Regents of the University of California
    Inventors: John Harada, Sandra Stone, Julie Pelletier
  • Publication number: 20070011760
    Abstract: The invention provides methods of controlling endosperm development in plants.
    Type: Application
    Filed: October 20, 2005
    Publication date: January 11, 2007
    Applicant: The Regents of the University of California
    Inventors: Robert Fischer, Nir Ohad, Tomohiro Kiyosue, Ramin Yadegari, Linda Margossian, John Harada, Robert Goldberg
  • Patent number: 7138566
    Abstract: The present invention is directed to plant genetic engineering. In particular, it relates to methods of modulating cytokinin related processes in a plant and selecting a plant having a phenotype associated with an altered cytokinin-related process.
    Type: Grant
    Filed: June 21, 2002
    Date of Patent: November 21, 2006
    Assignee: Regents of the University of California
    Inventors: John Harada, Sandra Stone, Julie Pelletier
  • Patent number: 7049488
    Abstract: The invention provides methods of controlling endosperm development in plants.
    Type: Grant
    Filed: August 6, 2002
    Date of Patent: May 23, 2006
    Assignee: The Regents of the University of California
    Inventors: Robert L. Fischer, Nir Ohad, Tomohiro Kiyosue, Ramin Yadegari, Linda Margossian, John Harada, Robert B. Goldberg
  • Patent number: 7029917
    Abstract: The present invention provides polynucleotides that control endosperm development in plants.
    Type: Grant
    Filed: May 1, 1998
    Date of Patent: April 18, 2006
    Assignee: The Regents of the University of California
    Inventors: Robert L. Fischer, Nir Ohad, Tomohiro Kiyosue, Ramin Yadegari, Linda Margossian, John Harada, Robert B. Goldberg
  • Patent number: 6860028
    Abstract: An alignment device includes a crossbar and two brackets. Each one of the two brackets includes at least one guide hole, with each guide hole having a front opening. The crossbar couples the two brackets and defines a connector opening. The alignment device also includes two connector alignment posts. Each one of the two connector alignment posts has a first end coupled to the crossbar and an opposing end protruding into the connector opening. A method of connecting a circuit card to a mid plane and a computer including the alignment device also are described.
    Type: Grant
    Filed: April 30, 2003
    Date of Patent: March 1, 2005
    Assignee: Sun Microsystems, Inc.
    Inventors: Glenn P. Charest, William L. Grouell, John A. Harada
  • Patent number: D823954
    Type: Grant
    Filed: June 29, 2016
    Date of Patent: July 24, 2018
    Assignee: Active Ideas LLC
    Inventors: John Harada, John Godoy
  • Patent number: D823955
    Type: Grant
    Filed: June 29, 2016
    Date of Patent: July 24, 2018
    Assignee: Active Ideas LLC
    Inventors: John Harada, John Godoy