Patents by Inventor John Hogeboom
John Hogeboom has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9405511Abstract: A FIR transmit architecture uses multiple driver divisions to allow signals with different delays to be summed into the output signal by the driver itself. The architecture includes a first multiplexer, a plurality of delay cells, a plurality of sign blocks, a switch block, a second multiplexer, and a plurality of drivers.Type: GrantFiled: October 27, 2014Date of Patent: August 2, 2016Assignees: STMICROELECTRONICS (CANADA) INC., STIMICROELECTRONICS S.R.L.Inventors: John Hogeboom, Hock Khor, Matteo Alessio Traldi, Anton Pelteshki
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Publication number: 20150074160Abstract: A FIR transmit architecture uses multiple driver divisions to allow signals with different delays to be summed into the output signal by the driver itself. The architecture includes a first multiplexer, a plurality of delay cells, a plurality of sign blocks, a switch block, a second multiplexer, and a plurality of drivers.Type: ApplicationFiled: October 27, 2014Publication date: March 12, 2015Inventors: JOHN HOGEBOOM, HOCK KHOR, MATTEO ALESSIO TRALDI, ANTON PELTESHKI
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Patent number: 8886694Abstract: A FIR transmit architecture uses multiple driver divisions to allow signals with different delays to be summed into the output signal by the driver itself. The architecture includes a first multiplexer, a plurality of delay cells, a plurality of sign blocks, a switch block, a second multiplexer, and a plurality of drivers.Type: GrantFiled: December 22, 2011Date of Patent: November 11, 2014Assignees: STMicroelectronics (Canada) Inc., STMicroelectronics S.R.L.Inventors: John Hogeboom, Hock Khor, Matteo Traldi, Anton Pelteshki
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Patent number: 8731041Abstract: A DFE filter includes an input, a first filter loop coupled to the input for providing an odd bit-stream, and a second filter loop coupled to the input for providing an even bit-stream, wherein the first and second filter loops are identical and interleaved.Type: GrantFiled: April 18, 2012Date of Patent: May 20, 2014Assignee: STMicroelectronics (Canada) Inc.Inventors: Anton Pelteshki, John Hogeboom
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Publication number: 20120269305Abstract: A receive channel offset correction scheme utilizes “eye edge” samplers and demultiplexers already present and essential for operation of the CDR algorithm, and adds only simple word-rate logic, with no new analog circuitry. The result is the ability to precisely determine the offset polarity as well as to get an approximate immediate measure of the offset magnitude. The offset detected includes all of the analog circuitry in the channel, including the samplers themselves.Type: ApplicationFiled: April 18, 2012Publication date: October 25, 2012Applicant: STMicroelectronics (Canada) Inc.Inventors: John Hogeboom, Pat Hogeboom-Nivera
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Publication number: 20120269255Abstract: A DFE filter includes an input, a first filter loop coupled to the input for providing an odd bit-stream, and a second filter loop coupled to the input for providing an even bit-stream, wherein the first and second filter loops are identical and interleaved.Type: ApplicationFiled: April 18, 2012Publication date: October 25, 2012Applicant: STMicroelectronics (Canada) Inc.Inventors: Anton Pelteshki, John Hogeboom
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Publication number: 20120268177Abstract: A fractional rate LC VCO and compensating divider circuit to avoid bit-rate interference includes an LC PLL having an input for receiving a reference clock signal, an N-stage ring VCO with rotating injection having an input coupled to an output of the LC PLL and an output for providing an output clock signal, a first divider circuit having an input coupled to an output of the N-stage ring VCO and an output coupled to the LC PLL, a second divider circuit having an input coupled to the output of the LC PLL, and an M-stage reference ring PLL having an input coupled to an output of the second divider and an output coupled to the N-stage ring VCO.Type: ApplicationFiled: April 18, 2012Publication date: October 25, 2012Applicant: STMicroelectronics (Canada) Inc.Inventors: John Hogeboom, Pat Hogeboom-Nivera, Anton Pelteshki
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Patent number: 8228972Abstract: A first device transmits data over a first branch of a communications link toward a second device. That second device loops the received data pattern back over a second branch of the communications link. A bit error rate of the looped back data pattern is determined and a pre-emphasis applied to the transmitted data pattern is adjusted in response thereto. The first device further perturbs the data pattern communications signal so as to increase the bit error rate. The pre-emphasis is adjusted so as to reduce the determined bit error rate in the looped back data pattern in the presence of the perturbation. The steps for perturbing the signal and adjusting the pre-emphasis are iteratively performed, with the perturbation of the signal increasing with each iteration and adjustment of the pre-emphasis being refined with each iteration. The signal is perturbing by injecting modulation jitter into the signal (increasing each iteration) and adjusting amplitude of the signal (decreasing each iteration).Type: GrantFiled: June 4, 2008Date of Patent: July 24, 2012Assignee: STMicroelectronics, Inc.Inventors: Davide Tonietto, John Hogeboom
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Publication number: 20120166505Abstract: A FIR transmit architecture uses multiple driver divisions to allow signals with different delays to be summed into the output signal by the driver itself. The architecture includes a first multiplexer, a plurality of delay cells, a plurality of sign blocks, a switch block, a second multiplexer, and a plurality of drivers.Type: ApplicationFiled: December 22, 2011Publication date: June 28, 2012Applicants: STMicroelectronics Srl, STMicroelectronics (Canada) Inc.Inventors: John Hogeboom, Hock Khor, Matteo Traldi, Anton Pelteshki
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Publication number: 20120161827Abstract: A clock circuit includes a frequency or phase comparator for receiving a reference clock signal, an LC VCO coupled to the comparator, a feedback divider coupled between the LC VCO and the comparator, a clock distribution chain coupled to the feedback divider and the first VCO, and a DLL or injection-locked ring-VCO coupled to the clock distribution chain for providing a plurality of phased output clock signals.Type: ApplicationFiled: December 27, 2011Publication date: June 28, 2012Applicant: STMicroelectronics (Canada) Inc.Inventors: Paul Madeira, John Hogeboom, Pat Hogeboom-Nivera
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Publication number: 20100097087Abstract: A built-in self test for receiver operation is provided through a testing method that evaluates characteristics of a received signal eye diagram. The receiver receives a serial data signal and applies compensation to that received serial data signal to generate a compensated serial data signal. The properties of an eye diagram associated with the compensated serial data signal are measured. In this context, certain desired eye diagram properties are characterized by parameters indicative of pass/fail criteria for receiver testing. The measured eye diagram properties are then compared against the parameters. A receiver testing conclusion signal is then output based on results of the comparison.Type: ApplicationFiled: October 20, 2008Publication date: April 22, 2010Applicant: STMicroelectronics, Inc.Inventors: John Hogeboom, Davide Tonietto
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Publication number: 20090304054Abstract: A first device transmits data over a first branch of a communications link toward a second device. That second device loops the received data pattern back over a second branch of the communications link. A bit error rate of the looped back data pattern is determined and a pre-emphasis applied to the transmitted data pattern is adjusted in response thereto. The first device further perturbs the data pattern communications signal so as to increase the bit error rate. The pre-emphasis is adjusted so as to reduce the determined bit error rate in the looped back data pattern in the presence of the perturbation. The steps for perturbing the signal and adjusting the pre-emphasis are iteratively performed, with the perturbation of the signal increasing with each iteration and adjustment of the pre-emphasis being refined with each iteration. The signal is perturbing by injecting modulation jitter into the signal (increasing each iteration) and adjusting amplitude of the signal (decreasing each iteration).Type: ApplicationFiled: June 4, 2008Publication date: December 10, 2009Applicant: STMicroelectronics, Inc.Inventors: Davide Tonietto, John Hogeboom