Patents by Inventor John J. Bush

John J. Bush has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11856182
    Abstract: A method for determining the magnitude of leakage in a subscriber's premises CATV installation; a frequency multiplexer for coupling between an antenna and a receiver for the multiplexed frequencies; and, a method for a technician to certify a CATV subscriber's premises for the provision of CATV services are disclosed.
    Type: Grant
    Filed: November 29, 2021
    Date of Patent: December 26, 2023
    Assignee: VIAVI SOLUTIONS INC.
    Inventors: Terry W. Bush, John J. Bush, Dexin Sun
  • Patent number: 11509954
    Abstract: The existing Data Over Cable Service Interface Specification (DOCSIS) carriers generated by field test equipment or by the CATV subscriber modems are used to determine the amplitude response of the return band in a CATV system.
    Type: Grant
    Filed: March 9, 2020
    Date of Patent: November 22, 2022
    Assignee: VIAVI SOLUTIONS INC.
    Inventors: John J. Bush, Gary W. Sinde
  • Publication number: 20220217327
    Abstract: A method for determining the magnitude of leakage in a subscriber's premises CATV installation; a frequency multiplexer for coupling between an antenna and a receiver for the multiplexed frequencies; and, a method for a technician to certify a CATV subscriber's premises for the provision of CATV services are disclosed.
    Type: Application
    Filed: November 29, 2021
    Publication date: July 7, 2022
    Applicant: VIAVI SOLUTIONS INC.
    Inventors: Terry W. Bush, John J. Bush, Dexin Sun
  • Publication number: 20220109612
    Abstract: An intelligent monitoring and testing system for a cable network determines measurements for a cable plant (CP), including cable modems (CMs) and common network elements, Metrics determined from the measurements are analyzed to detect a service issue and a service sub-issue. Machine learning is applied to the metrics and other related data to determine an optimized workflow for diagnosing, locating, and remediating the service issue and service sub-issue.
    Type: Application
    Filed: October 4, 2021
    Publication date: April 7, 2022
    Applicant: VIAVI SOLUTIONS INC.
    Inventors: John J. BUSH, Robert J. FLASK, Raleigh Benton STELLE, IV, Alvin R. RUTH
  • Patent number: 11212517
    Abstract: A method for determining the magnitude of leakage in a subscriber's premises CATV installation; a frequency multiplexer for coupling between an antenna and a receiver for the multiplexed frequencies; and, a method for a technician to certify a CATV subscriber's premises for the provision of CATV services are disclosed.
    Type: Grant
    Filed: August 4, 2020
    Date of Patent: December 28, 2021
    Assignee: VIAVI SOLUTIONS INC.
    Inventors: Terry W. Bush, John J. Bush, Dexin Sun
  • Publication number: 20210120229
    Abstract: A method for determining the magnitude of leakage in a subscriber's premises CATV installation; a frequency multiplexer for coupling between an antenna and a receiver for the multiplexed frequencies; and, a method for a technician to certify a CATV subscriber's premises for the provision of CATV services are disclosed.
    Type: Application
    Filed: August 4, 2020
    Publication date: April 22, 2021
    Applicant: VIAVI SOLUTIONS INC.
    Inventors: Terry W. Bush, John J. Bush, Dexin Sun
  • Publication number: 20200351542
    Abstract: The existing Data Over Cable Service Interface Specification (DOCSIS) carriers generated by field test equipment or by the CATV subscriber modems are used to determine the amplitude response of the return band in a CATV system.
    Type: Application
    Filed: March 9, 2020
    Publication date: November 5, 2020
    Applicant: VIAVI SOLUTIONS INC.
    Inventors: John J. BUSH, Gary W. Sinde
  • Patent number: 10771777
    Abstract: A method for determining the magnitude of leakage in a subscriber's premises CATV installation; a frequency multiplexer for coupling between an antenna and a receiver for the multiplexed frequencies; and, a method for a technician to certify a CATV subscriber's premises for the provision of CATV services are disclosed.
    Type: Grant
    Filed: June 10, 2019
    Date of Patent: September 8, 2020
    Assignee: VIAVI SOLUTIONS, INC.
    Inventors: Terry W. Bush, John J. Bush, Dexin Sun
  • Patent number: 10728539
    Abstract: A method for determining the magnitude of leakage in a subscriber's premises CATV installation; a frequency multiplexer for coupling between an antenna and a receiver for the multiplexed frequencies; and, a method for a technician to certify a CATV subscriber's premises for the provision of CATV services are disclosed.
    Type: Grant
    Filed: October 30, 2018
    Date of Patent: July 28, 2020
    Assignee: VIAVI SOLUTIONS, INC.
    Inventors: Terry W. Bush, John J. Bush, Dexin Sun
  • Patent number: 10623809
    Abstract: The existing Data Over Cable Service Interface Specification (DOCSIS) carriers generated by field test equipment or by the CATV subscriber modems are used to determine the amplitude response of the return band in a CATV system.
    Type: Grant
    Filed: August 19, 2015
    Date of Patent: April 14, 2020
    Assignee: VIAVI SOLUTIONS, INC.
    Inventors: John J. Bush, Gary W. Sinde
  • Publication number: 20190313089
    Abstract: A method for determining the magnitude of leakage in a subscriber's premises CATV installation; a frequency multiplexer for coupling between an antenna and a receiver for the multiplexed frequencies; and, a method for a technician to certify a CATV subscriber's premises for the provision of CATV services are disclosed.
    Type: Application
    Filed: June 10, 2019
    Publication date: October 10, 2019
    Inventors: Terry W. BUSH, John J. BUSH, Dexin SUN
  • Publication number: 20190132585
    Abstract: A method for determining the magnitude of leakage in a subscriber's premises CATV installation; a frequency multiplexer for coupling between an antenna and a receiver for the multiplexed frequencies; and, a method for a technician to certify a CATV subscriber's premises for the provision of CATV services are disclosed.
    Type: Application
    Filed: October 30, 2018
    Publication date: May 2, 2019
    Inventors: Terry W. Bush, John J. Bush, Dexin Sun
  • Patent number: 9654218
    Abstract: In a communication network, a node at a subscriber premises includes an input/output (I/O) port, and a device for monitoring a subscriber premises. The device includes an upstream signal path including a first switch, a downstream signal path, and a controller having an input/output (I/O) port coupled to the I/O port of the node, and a first output port. The first switch is coupled to the first output port selectively to complete the upstream signal path.
    Type: Grant
    Filed: March 21, 2014
    Date of Patent: May 16, 2017
    Assignee: Trilithic, Inc.
    Inventors: Terry W. Bush, Gary W. Sinde, John J. Bush
  • Publication number: 20160057479
    Abstract: The existing Data Over Cable Service Interface Specification (DOCSIS) carriers generated by field test equipment or by the CATV subscriber modems are used to determine the amplitude response of the return band in a CATV system.
    Type: Application
    Filed: August 19, 2015
    Publication date: February 25, 2016
    Inventors: John J. Bush, Gary W. Sinde
  • Patent number: 6977195
    Abstract: For characterizing bulk leakage current of a junction, a center junction surrounded by an isolation structure is formed with a first depth. In addition, at least one periphery junction having a second depth greater than the first depth is formed in a portion of the center junction adjacent the isolation structure. A junction silicide is formed with the center and periphery junctions. The magnitude of a reverse-bias voltage across the junction silicide and the P-well is incremented for determining a critical magnitude of the reverse-bias when current through the junction silicide and the P-well reaches a threshold current density.
    Type: Grant
    Filed: August 16, 2004
    Date of Patent: December 20, 2005
    Assignee: FASL, LLC
    Inventors: John J. Bush, Wen-Jie Qi, Robert Dawson
  • Patent number: 6469316
    Abstract: Various embodiments of a test circuit and methods of fabricating and using the same are provided. In one aspect, a test circuit includes a semiconductor substrate and a mask thereon that has an opening to enable impurity doping of selected portions of the test circuit. A plurality of circuit devices are provided on the substrate that have respective active regions positioned at staggered known distances from the mask opening. Each of the plurality of circuit devices has a gate electrode that extends to the opening and has a first impurity region of a first conductivity type and a second impurity region of a second and opposite conductivity type. Where the predicted on-state output current of a given circuit device exceeds an actual output current of the given circuit device, there is indication of an overlap between the first and second impurity regions of the gate electrode of the given device.
    Type: Grant
    Filed: January 8, 2001
    Date of Patent: October 22, 2002
    Assignee: Advanced Micro Devices, Inc.
    Inventors: John J. Bush, Mark I. Gardner, David E. Brown
  • Patent number: 6429052
    Abstract: The present invention is directed to a method for manufacturing a high performance transistor device with a reduced width or “t-shaped” gate electrode. The method disclosed herein comprises forming a gate insulation layer on a semiconducting substrate, forming a layer of polysilicon above the gate insulation layer, forming a layer of amorphous silicon above the layer of polysilicon, and patterning the layer of polysilicon and the layer of amorphous silicon to define a gate structure. The method further comprises reducing the width of the layer of polysilicon and the layer of amorphous silicon by performing an oxidation process, whereby the layer of polysilicon has a post-oxidation width that is less than the post-oxidation width of the layer of amorphous silicon, and forming a plurality of source/drain regions in the substrate adjacent the gate electrode of the device.
    Type: Grant
    Filed: November 13, 2000
    Date of Patent: August 6, 2002
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Mark I. Gardner, John J. Bush, Frederick N. Hause
  • Patent number: 6380554
    Abstract: The present invention advantageously provides a test structure and method for using electrical measurements to determine the overlay between successive layers of conductors lithographically patterned upon a semiconductor topography. According to an embodiment, a test structure is provided which includes first, second, and third conductive structures having first, second, and third corner regions, respectively. Alternatively, the conductive structures may include only a single conductive structure having three corner regions. Each corner region is bounded by a pair of outer lateral edges configured substantially perpendicular to one another. First, second, and third conductors are operably coupled to the first, second, and third corner regions, respectively, such that overlapping areas of the conductors arranged directly above the corner regions are substantially rectangular in shape. The layout design for the test structure specifies the targeted dimensions, x and y, of each overlapping area.
    Type: Grant
    Filed: June 8, 1998
    Date of Patent: April 30, 2002
    Assignee: Advanced Micro Devices, Inc.
    Inventors: John J. Bush, H. Jim Fulford, Jr., Mark I. Gardner
  • Patent number: 6359461
    Abstract: The present invention advantageously provides a test structure and method for determining the distinct characteristics of each transistor arranged in a densely packed configuration with other transistors. Formation of the test structure first involves forming gate conductors according to the configuration of the semiconductor topography whose device properties are being determined. That is, closely spaced gate conductors having relatively small lateral widths, i.e., physical gate lengths, are formed above a semiconductor substrate. All of the gate conductors except the one being tested are then etched from above the substrate. Source/drain implants which are self-aligned to the opposed sidewall surfaces of the gate conductor retained above the substrate are forwarded into the substrate. Absent the other gate conductors, the resulting source/drain regions may each have a larger lateral width greater than the distance between the pre-existing gate conductors.
    Type: Grant
    Filed: February 10, 1998
    Date of Patent: March 19, 2002
    Assignee: Advanced Micro Devices, Inc.
    Inventors: John J. Bush, Jon D. Cheek, H. Jim Fulford
  • Patent number: 6191446
    Abstract: A process is provided for forming a transistor in which the channel length is controlled by the depth of a trench etched into a semiconductor substrate. A masking layer extending across the substrate and a portion of the substrate are etched simultaneously to form the trench. A gate dielectric is formed upon the opposed sidewall surfaces of the trench. A pair of gate conductors are then formed upon the exposed lateral surfaces of the gate dielectric and the masking layer. Subsequently, an unmasked region of the substrate underneath the trench is implanted with dopant species and then annealed to form a source junction. The anneal temperature is preferably sufficient to cause the dopant species in the source junction to migrate laterally past the opposed sidewall surfaces of the trench. Drain junctions may subsequently be formed within the substrate a spaced distance above the source region on opposite sides of the trench.
    Type: Grant
    Filed: March 4, 1998
    Date of Patent: February 20, 2001
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Mark I. Gardner, John J. Bush, Jon D. Cheek