Patents by Inventor John J. Gill

John J. Gill has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11824247
    Abstract: A set of antenna geometries for use in integrated arrays at terahertz frequencies are described. Two fabrication techniques to construct such antennas are presented. The first technique uses an advanced laser micro-fabrication, allowing fabricating advanced 3D geometries. The second technique uses photolithographic processes, allowing the fabrication of arrays on a single wafer in parallel.
    Type: Grant
    Filed: May 19, 2020
    Date of Patent: November 21, 2023
    Assignee: CALIFORNIA INSTITUTE OF TECHNOLOGY
    Inventors: Goutam Chattopadhyay, Imran Mehdi, Choonsup Lee, John J. Gill, Cecile D. Jung-Kubiak, Nuria Llombart
  • Publication number: 20200313271
    Abstract: A set of antenna geometries for use in integrated arrays at terahertz frequencies are described. Two fabrication techniques to construct such antennas are presented. The first technique uses an advanced laser micro-fabrication, allowing fabricating advanced 3D geometries. The second technique uses photolithographic processes, allowing the fabrication of arrays on a single wafer in parallel.
    Type: Application
    Filed: May 19, 2020
    Publication date: October 1, 2020
    Applicant: California Institute of Technology
    Inventors: Goutam Chattopadhyay, Imran Mehdi, Choonsup Lee, John J. Gill, Cecile D. Jung-Kubiak, Nuria Llombart
  • Patent number: 10693210
    Abstract: A set of antenna geometries for use in integrated arrays at terahertz frequencies are described. Two fabrication techniques to construct such antennas are presented. The first technique uses an advanced laser micro-fabrication, allowing fabricating advanced 3D geometries. The second technique uses photolithographic processes, allowing the fabrication of arrays on a single wafer in parallel.
    Type: Grant
    Filed: April 24, 2013
    Date of Patent: June 23, 2020
    Assignee: CALIFORNIA INSTITUTE OF TECHNOLOGY
    Inventors: Goutam Chattopadhyay, Imran Mehdi, Choonsup Lee, John J. Gill, Cecile D. Jung-Kubiak, Nuria Llombart
  • Patent number: 10100858
    Abstract: A silicon alignment pin is used to align successive layer of component made in semiconductor chips and/or metallic components to make easier the assembly of devices having a layered structure. The pin is made as a compressible structure which can be squeezed to reduce its outer diameter, have one end fit into a corresponding alignment pocket or cavity defined in a layer of material to be assembled into a layered structure, and then allowed to expand to produce an interference fit with the cavity. The other end can then be inserted into a corresponding cavity defined in a surface of a second layer of material that mates with the first layer. The two layers are in registry when the pin is mated to both. Multiple layers can be assembled to create a multilayer structure. Examples of such devices are presented.
    Type: Grant
    Filed: October 28, 2016
    Date of Patent: October 16, 2018
    Assignee: CALIFORNIA INSTITUTE OF TECHNOLOGY
    Inventors: Cecile Jung-Kubiak, Theodore Reck, Bertrand Thomas, Robert H. Lin, Alejandro Peralta, John J. Gill, Choonsup Lee, Jose V. Siles, Risaku Toda, Goutam Chattopadhyay, Ken B. Cooper, Imran Mehdi
  • Patent number: 9791321
    Abstract: A multi-pixel terahertz transceiver is constructed using a stack of semiconductor layers that communicate using vias defined within the semiconductor layers. By using a stack of semiconductor layers, the various electrical functions of each layer can be tested easily without having to assemble the entire transceiver. In addition, the design allows the production of a transceiver having pixels set 10 mm apart.
    Type: Grant
    Filed: May 24, 2013
    Date of Patent: October 17, 2017
    Assignee: California Institute of Technology
    Inventors: Goutam Chattopadhyay, Ken B. Cooper, Emmanuel Decrossas, John J. Gill, Cecile Jung-Kubiak, Choonsup Lee, Robert Lin, Imran Mehdi, Alejandro Peralta, Theodore Reck, Jose Siles
  • Publication number: 20170045065
    Abstract: A silicon alignment pin is used to align successive layer of component made in semiconductor chips and/or metallic components to make easier the assembly of devices having a layered structure. The pin is made as a compressible structure which can be squeezed to reduce its outer diameter, have one end fit into a corresponding alignment pocket or cavity defined in a layer of material to be assembled into a layered structure, and then allowed to expand to produce an interference fit with the cavity. The other end can then be inserted into a corresponding cavity defined in a surface of a second layer of material that mates with the first layer. The two layers are in registry when the pin is mated to both. Multiple layers can be assembled to create a multilayer structure. Examples of such devices are presented.
    Type: Application
    Filed: October 28, 2016
    Publication date: February 16, 2017
    Inventors: Cecile JUNG-KUBIAK, Theodore RECK, Bertrand THOMAS, Robert H. LIN, Alejandro PERALTA, John J. GILL, Choonsup LEE, Jose V. SILES, Risaku TODA, Goutam CHATTOPADHYAY, Ken B. COOPER, Imran MEHDI
  • Patent number: 9512863
    Abstract: A silicon alignment pin is used to align successive layers of components made in semiconductor chips and/or metallic components to make easier the assembly of devices having a layered structure. The pin is made as a compressible structure which can be squeezed to reduce its outer diameter, have one end fit into a corresponding alignment pocket or cavity defined in a layer of material to be assembled into a layered structure, and then allowed to expand to produce an interference fit with the cavity. The other end can then be inserted into a corresponding cavity defined in a surface of a second layer of material that mates with the first layer. The two layers are in registry when the pin is mated to both. Multiple layers can be assembled to create a multilayer structure. Examples of such devices are presented.
    Type: Grant
    Filed: April 26, 2013
    Date of Patent: December 6, 2016
    Assignee: CALIFORNIA INSTITUTE OF TECHNOLOGY
    Inventors: Cecile Jung-Kubiak, Theodore Reck, Bertrand Thomas, Robert H. Lin, Alejandro Peralta, John J. Gill, Choonsup Lee, Jose V. Siles, Risaku Toda, Goutam Chattopadhyay, Ken B. Cooper, Imran Mehdi
  • Publication number: 20150300884
    Abstract: A multi-pixel terahertz transceiver is constructed using a stack of semiconductor layers that communicate using vias defined within the semiconductor layers. By using a stack of semiconductor layers, the various electrical functions of each layer can be tested easily without having to assemble the entire transceiver. In addition, the design allows the production of a transceiver having pixels set 10 mm apart.
    Type: Application
    Filed: May 24, 2013
    Publication date: October 22, 2015
    Applicant: CALIFORNIA INSTITUTE OF TECHNOLOGY
    Inventors: Theodore Reck, Ken B. Cooper, Cecile Jung-Kubiak, Choonsup Lee, John J. Gill
  • Patent number: 8780012
    Abstract: An antenna element suitable for integrated arrays at terahertz frequencies is disclosed. The antenna element comprises an extended spherical (e.g. hemispherical) semiconductor lens, e.g. silicon, antenna fed by a leaky wave waveguide feed. The extended spherical lens comprises a substantially spherical lens adjacent a substantially planar lens extension. A couple of TE/TM leaky wave modes are excited in a resonant cavity formed between a ground plane and the substantially planar lens extension by a waveguide block coupled to the ground plane. Due to these modes, the primary feed radiates inside the lens with a directive pattern that illuminates a small sector of the lens. The antenna structure is compatible with known semiconductor fabrication technology and enables production of large format imaging arrays.
    Type: Grant
    Filed: June 30, 2010
    Date of Patent: July 15, 2014
    Assignee: California Institute of Technology
    Inventors: Nuria Llombart Juan, Choonsup Lee, Goutam Chattopadhyay, John J. Gill, Anders J. Skalare, Peter H. Siegel
  • Publication number: 20140147192
    Abstract: A silicon alignment pin is used to align successive layers of components made in semiconductor chips and/or metallic components to make easier the assembly of devices having a layered structure. The pin is made as a compressible structure which can be squeezed to reduce its outer diameter, have one end fit into a corresponding alignment pocket or cavity defined in a layer of material to be assembled into a layered structure, and then allowed to expand to produce an interference fit with the cavity. The other end can then be inserted into a corresponding cavity defined in a surface of a second layer of material that mates with the first layer. The two layers are in registry when the pin is mated to both. Multiple layers can be assembled to create a multilayer structure. Examples of such devices are presented.
    Type: Application
    Filed: April 26, 2013
    Publication date: May 29, 2014
    Applicant: CALIFORNIA INSTITUTE OF TECHNOLOGY
    Inventors: Cecile Jung-Kubiak, Theodore Reck, Bertrand Thomas, Robert H. Lin, Alejandro Peralta, John J. Gill, Choonsup Lee, Jose V. Siles, Risaku Toda, Goutam Chattopadhyay, Ken B. Cooper, Imran Mehdi
  • Publication number: 20140144009
    Abstract: A set of antenna geometries for use in integrated arrays at terahertz frequencies are described. Two fabrication techniques to construct such antennas are presented. The first technique uses an advanced laser micro-fabrication, allowing fabricating advanced 3D geometries. The second technique uses photolithographic processes, allowing the fabrication of arrays on a single wafer in parallel.
    Type: Application
    Filed: April 24, 2013
    Publication date: May 29, 2014
    Applicant: CALIFORNIA INSTITUTE OF TECHNOLOGY
    Inventors: Goutam CHATTOPADHYAY, Imran Mehdi, Choonsup Lee, John J. Gill, Cecile Jung-Kubiak, Nuria Llombart
  • Patent number: 8693973
    Abstract: A coplanar waveguide (CPW) based subharmonic mixer working at 670 GHz using GaAs Schottky diodes. One example of the mixer has a LO input, an RF input and an IF output. Another possible mixer has a LO input, and IF input and an RF output. Each input or output is connected to a coplanar waveguide with a matching network. A pair of antiparallel diodes provides a signal at twice the LO frequency, which is then mixed with a second signal to provide signals having sum and difference frequencies. The output signal of interest is received after passing through a bandpass filter tuned to the frequency range of interest.
    Type: Grant
    Filed: May 2, 2012
    Date of Patent: April 8, 2014
    Assignee: California Institute of Technology
    Inventors: Goutam Chattopadhyay, Erich T. Schlecht, Choonsup Lee, Robert H. Lin, John J. Gill, Seth Sin, Imran Mehdi
  • Publication number: 20120280742
    Abstract: A coplanar waveguide (CPW) based subharmonic mixer working at 670 GHz using GaAs Schottky diodes. One example of the mixer has a LO input, an RF input and an IF output. Another possible mixer has a LO input, and IF input and an RF output. Each input or output is connected to a coplanar waveguide with a matching network. A pair of antiparallel diodes provides a signal at twice the LO frequency, which is then mixed with a second signal to provide signals having sum and difference frequencies. The output signal of interest is received after passing through a bandpass filter tuned to the frequency range of interest.
    Type: Application
    Filed: May 2, 2012
    Publication date: November 8, 2012
    Applicant: California Institute of Technology
    Inventors: Goutam Chattopadhyay, Erich T. Schlecht, Choonsup Lee, Robert H. Lin, John J. Gill, Seth Sin, Imran Mehdi
  • Publication number: 20100328779
    Abstract: An antenna element suitable for integrated arrays at terahertz frequencies is disclosed. The antenna element comprises an extended spherical (e.g. hemispherical) semiconductor lens, e.g. silicon, antenna fed by a leaky wave waveguide feed. The extended spherical lens comprises a substantially spherical lens adjacent a substantially planar lens extension. A couple of TE/TM leaky wave modes are excited in a resonant cavity formed between a ground plane and the substantially planar lens extension by a waveguide block coupled to the ground plane. Due to these modes, the primary feed radiates inside the lens with a directive pattern that illuminates a small sector of the lens. The antenna structure is compatible with known semiconductor fabrication technology and enables production of large format imaging arrays.
    Type: Application
    Filed: June 30, 2010
    Publication date: December 30, 2010
    Applicant: California Institute of Technolology
    Inventors: Nuria Llombart Juan, Choonsup Lee, Goutam Chattopadhyay, John J. Gill, Anders Skalare, Peter H. Siegel