Patents by Inventor John J. Gill
John J. Gill has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11824247Abstract: A set of antenna geometries for use in integrated arrays at terahertz frequencies are described. Two fabrication techniques to construct such antennas are presented. The first technique uses an advanced laser micro-fabrication, allowing fabricating advanced 3D geometries. The second technique uses photolithographic processes, allowing the fabrication of arrays on a single wafer in parallel.Type: GrantFiled: May 19, 2020Date of Patent: November 21, 2023Assignee: CALIFORNIA INSTITUTE OF TECHNOLOGYInventors: Goutam Chattopadhyay, Imran Mehdi, Choonsup Lee, John J. Gill, Cecile D. Jung-Kubiak, Nuria Llombart
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Publication number: 20200313271Abstract: A set of antenna geometries for use in integrated arrays at terahertz frequencies are described. Two fabrication techniques to construct such antennas are presented. The first technique uses an advanced laser micro-fabrication, allowing fabricating advanced 3D geometries. The second technique uses photolithographic processes, allowing the fabrication of arrays on a single wafer in parallel.Type: ApplicationFiled: May 19, 2020Publication date: October 1, 2020Applicant: California Institute of TechnologyInventors: Goutam Chattopadhyay, Imran Mehdi, Choonsup Lee, John J. Gill, Cecile D. Jung-Kubiak, Nuria Llombart
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Patent number: 10693210Abstract: A set of antenna geometries for use in integrated arrays at terahertz frequencies are described. Two fabrication techniques to construct such antennas are presented. The first technique uses an advanced laser micro-fabrication, allowing fabricating advanced 3D geometries. The second technique uses photolithographic processes, allowing the fabrication of arrays on a single wafer in parallel.Type: GrantFiled: April 24, 2013Date of Patent: June 23, 2020Assignee: CALIFORNIA INSTITUTE OF TECHNOLOGYInventors: Goutam Chattopadhyay, Imran Mehdi, Choonsup Lee, John J. Gill, Cecile D. Jung-Kubiak, Nuria Llombart
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Patent number: 10100858Abstract: A silicon alignment pin is used to align successive layer of component made in semiconductor chips and/or metallic components to make easier the assembly of devices having a layered structure. The pin is made as a compressible structure which can be squeezed to reduce its outer diameter, have one end fit into a corresponding alignment pocket or cavity defined in a layer of material to be assembled into a layered structure, and then allowed to expand to produce an interference fit with the cavity. The other end can then be inserted into a corresponding cavity defined in a surface of a second layer of material that mates with the first layer. The two layers are in registry when the pin is mated to both. Multiple layers can be assembled to create a multilayer structure. Examples of such devices are presented.Type: GrantFiled: October 28, 2016Date of Patent: October 16, 2018Assignee: CALIFORNIA INSTITUTE OF TECHNOLOGYInventors: Cecile Jung-Kubiak, Theodore Reck, Bertrand Thomas, Robert H. Lin, Alejandro Peralta, John J. Gill, Choonsup Lee, Jose V. Siles, Risaku Toda, Goutam Chattopadhyay, Ken B. Cooper, Imran Mehdi
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Patent number: 9791321Abstract: A multi-pixel terahertz transceiver is constructed using a stack of semiconductor layers that communicate using vias defined within the semiconductor layers. By using a stack of semiconductor layers, the various electrical functions of each layer can be tested easily without having to assemble the entire transceiver. In addition, the design allows the production of a transceiver having pixels set 10 mm apart.Type: GrantFiled: May 24, 2013Date of Patent: October 17, 2017Assignee: California Institute of TechnologyInventors: Goutam Chattopadhyay, Ken B. Cooper, Emmanuel Decrossas, John J. Gill, Cecile Jung-Kubiak, Choonsup Lee, Robert Lin, Imran Mehdi, Alejandro Peralta, Theodore Reck, Jose Siles
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Publication number: 20170045065Abstract: A silicon alignment pin is used to align successive layer of component made in semiconductor chips and/or metallic components to make easier the assembly of devices having a layered structure. The pin is made as a compressible structure which can be squeezed to reduce its outer diameter, have one end fit into a corresponding alignment pocket or cavity defined in a layer of material to be assembled into a layered structure, and then allowed to expand to produce an interference fit with the cavity. The other end can then be inserted into a corresponding cavity defined in a surface of a second layer of material that mates with the first layer. The two layers are in registry when the pin is mated to both. Multiple layers can be assembled to create a multilayer structure. Examples of such devices are presented.Type: ApplicationFiled: October 28, 2016Publication date: February 16, 2017Inventors: Cecile JUNG-KUBIAK, Theodore RECK, Bertrand THOMAS, Robert H. LIN, Alejandro PERALTA, John J. GILL, Choonsup LEE, Jose V. SILES, Risaku TODA, Goutam CHATTOPADHYAY, Ken B. COOPER, Imran MEHDI
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Patent number: 9512863Abstract: A silicon alignment pin is used to align successive layers of components made in semiconductor chips and/or metallic components to make easier the assembly of devices having a layered structure. The pin is made as a compressible structure which can be squeezed to reduce its outer diameter, have one end fit into a corresponding alignment pocket or cavity defined in a layer of material to be assembled into a layered structure, and then allowed to expand to produce an interference fit with the cavity. The other end can then be inserted into a corresponding cavity defined in a surface of a second layer of material that mates with the first layer. The two layers are in registry when the pin is mated to both. Multiple layers can be assembled to create a multilayer structure. Examples of such devices are presented.Type: GrantFiled: April 26, 2013Date of Patent: December 6, 2016Assignee: CALIFORNIA INSTITUTE OF TECHNOLOGYInventors: Cecile Jung-Kubiak, Theodore Reck, Bertrand Thomas, Robert H. Lin, Alejandro Peralta, John J. Gill, Choonsup Lee, Jose V. Siles, Risaku Toda, Goutam Chattopadhyay, Ken B. Cooper, Imran Mehdi
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Publication number: 20150300884Abstract: A multi-pixel terahertz transceiver is constructed using a stack of semiconductor layers that communicate using vias defined within the semiconductor layers. By using a stack of semiconductor layers, the various electrical functions of each layer can be tested easily without having to assemble the entire transceiver. In addition, the design allows the production of a transceiver having pixels set 10 mm apart.Type: ApplicationFiled: May 24, 2013Publication date: October 22, 2015Applicant: CALIFORNIA INSTITUTE OF TECHNOLOGYInventors: Theodore Reck, Ken B. Cooper, Cecile Jung-Kubiak, Choonsup Lee, John J. Gill
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Patent number: 8780012Abstract: An antenna element suitable for integrated arrays at terahertz frequencies is disclosed. The antenna element comprises an extended spherical (e.g. hemispherical) semiconductor lens, e.g. silicon, antenna fed by a leaky wave waveguide feed. The extended spherical lens comprises a substantially spherical lens adjacent a substantially planar lens extension. A couple of TE/TM leaky wave modes are excited in a resonant cavity formed between a ground plane and the substantially planar lens extension by a waveguide block coupled to the ground plane. Due to these modes, the primary feed radiates inside the lens with a directive pattern that illuminates a small sector of the lens. The antenna structure is compatible with known semiconductor fabrication technology and enables production of large format imaging arrays.Type: GrantFiled: June 30, 2010Date of Patent: July 15, 2014Assignee: California Institute of TechnologyInventors: Nuria Llombart Juan, Choonsup Lee, Goutam Chattopadhyay, John J. Gill, Anders J. Skalare, Peter H. Siegel
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Publication number: 20140147192Abstract: A silicon alignment pin is used to align successive layers of components made in semiconductor chips and/or metallic components to make easier the assembly of devices having a layered structure. The pin is made as a compressible structure which can be squeezed to reduce its outer diameter, have one end fit into a corresponding alignment pocket or cavity defined in a layer of material to be assembled into a layered structure, and then allowed to expand to produce an interference fit with the cavity. The other end can then be inserted into a corresponding cavity defined in a surface of a second layer of material that mates with the first layer. The two layers are in registry when the pin is mated to both. Multiple layers can be assembled to create a multilayer structure. Examples of such devices are presented.Type: ApplicationFiled: April 26, 2013Publication date: May 29, 2014Applicant: CALIFORNIA INSTITUTE OF TECHNOLOGYInventors: Cecile Jung-Kubiak, Theodore Reck, Bertrand Thomas, Robert H. Lin, Alejandro Peralta, John J. Gill, Choonsup Lee, Jose V. Siles, Risaku Toda, Goutam Chattopadhyay, Ken B. Cooper, Imran Mehdi
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Publication number: 20140144009Abstract: A set of antenna geometries for use in integrated arrays at terahertz frequencies are described. Two fabrication techniques to construct such antennas are presented. The first technique uses an advanced laser micro-fabrication, allowing fabricating advanced 3D geometries. The second technique uses photolithographic processes, allowing the fabrication of arrays on a single wafer in parallel.Type: ApplicationFiled: April 24, 2013Publication date: May 29, 2014Applicant: CALIFORNIA INSTITUTE OF TECHNOLOGYInventors: Goutam CHATTOPADHYAY, Imran Mehdi, Choonsup Lee, John J. Gill, Cecile Jung-Kubiak, Nuria Llombart
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Patent number: 8693973Abstract: A coplanar waveguide (CPW) based subharmonic mixer working at 670 GHz using GaAs Schottky diodes. One example of the mixer has a LO input, an RF input and an IF output. Another possible mixer has a LO input, and IF input and an RF output. Each input or output is connected to a coplanar waveguide with a matching network. A pair of antiparallel diodes provides a signal at twice the LO frequency, which is then mixed with a second signal to provide signals having sum and difference frequencies. The output signal of interest is received after passing through a bandpass filter tuned to the frequency range of interest.Type: GrantFiled: May 2, 2012Date of Patent: April 8, 2014Assignee: California Institute of TechnologyInventors: Goutam Chattopadhyay, Erich T. Schlecht, Choonsup Lee, Robert H. Lin, John J. Gill, Seth Sin, Imran Mehdi
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Publication number: 20120280742Abstract: A coplanar waveguide (CPW) based subharmonic mixer working at 670 GHz using GaAs Schottky diodes. One example of the mixer has a LO input, an RF input and an IF output. Another possible mixer has a LO input, and IF input and an RF output. Each input or output is connected to a coplanar waveguide with a matching network. A pair of antiparallel diodes provides a signal at twice the LO frequency, which is then mixed with a second signal to provide signals having sum and difference frequencies. The output signal of interest is received after passing through a bandpass filter tuned to the frequency range of interest.Type: ApplicationFiled: May 2, 2012Publication date: November 8, 2012Applicant: California Institute of TechnologyInventors: Goutam Chattopadhyay, Erich T. Schlecht, Choonsup Lee, Robert H. Lin, John J. Gill, Seth Sin, Imran Mehdi
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Publication number: 20100328779Abstract: An antenna element suitable for integrated arrays at terahertz frequencies is disclosed. The antenna element comprises an extended spherical (e.g. hemispherical) semiconductor lens, e.g. silicon, antenna fed by a leaky wave waveguide feed. The extended spherical lens comprises a substantially spherical lens adjacent a substantially planar lens extension. A couple of TE/TM leaky wave modes are excited in a resonant cavity formed between a ground plane and the substantially planar lens extension by a waveguide block coupled to the ground plane. Due to these modes, the primary feed radiates inside the lens with a directive pattern that illuminates a small sector of the lens. The antenna structure is compatible with known semiconductor fabrication technology and enables production of large format imaging arrays.Type: ApplicationFiled: June 30, 2010Publication date: December 30, 2010Applicant: California Institute of TechnolologyInventors: Nuria Llombart Juan, Choonsup Lee, Goutam Chattopadhyay, John J. Gill, Anders Skalare, Peter H. Siegel