Abstract: A test system in an integrated circuit includes a boundary scan cell. The boundary scan cell includes a first storage element and a second storage element connected in series with the first storage element. The boundary scan cell also includes initialization logic connected between an output of the first storage element and an input of the second storage element. The initialization logic provides the output of the first storage element to the input of the second storage element unchanged during a first operating state, and provides an inverted version of the output of the first storage element to the input of the second storage element during a second operating state.

Abstract: A test system in an integrated circuit includes a boundary scan cell. The boundary scan cell includes a first storage element and a second storage element connected in series with the first storage element. The boundary scan cell also includes initialization logic connected between an output of the first storage element and an input of the second storage element. The initialization logic provides the output of the first storage element to the input of the second storage element unchanged during a first operating state, and provides an inverted version of the output of the first storage element to the input of the second storage element during a second operating state.

Abstract: A microprogram controller selects a sequence of low, gate level instructions (microcode) to execute a higher level (assembly language level) instruction. The controller includes a plurality of accessing elements for accessing a microinstruction from a corresponding plurality of different possible blocks of a microprogram store. All accessing elements are executed in parallel to provide a plurality of possible microinstructions. Control logic selects which one of the three accessed microinstructions is to be used next in sequence. The parallel nature of this process is fast. A unique instruction set minimizes the number of gates required for microcode storage. A subset of these instructions increase the efficiency of the microcode in terms of both the number of microinstructions required to perform a function and the microcode store address space-consumed by those microinstructions.