Abstract: An apparatus comprising a first circuit and a second circuit. The first circuit may comprise a control circuit and an oscillator. The control circuit may be configured to generate a control signal in response to a first reference signal and a second reference signal. The oscillator may be configured to generate the second reference signal in response to the control signal and a timing signal. The control signal is generally held when the first reference signal is lost. The second circuit may be configured to generate one or more output signals in response to the second reference signal and one of the one or more output signals. The one or more output signals may have a controlled delay with respect to the first reference signal.

Abstract: An apparatus comprising a first circuit and a second circuit. The first circuit may be configured to receive a first reference signal and generate a second reference signal. A frequency and a phase of the second reference signal may be (i) adjusted in response to the first reference signal and (ii) held when the first reference signal is lost. The second circuit may be configured to generate one or more output signals in response to the second reference signal and one of the one or more output signals. The one or more output signals may have a controlled and/or substantially zero delay with respect to the first reference signal.

Abstract: In one embodiment, a first circuit is configured to receive an input reference signal and a feedback signal, and present a reference clock signal based on a difference (e.g., phase difference) between the input reference signal and the feedback signal. The first circuit is further configured to present the reference clock signal even when the reference signal is disrupted. A frequency divider may be employed to scale the frequency of the feedback signal. The reference clock signal may be presented to another circuit to generate one or more output clock signals that are phase-locked to the reference clock signal, for example.

Abstract: A dual dot clock signal generator consisting of two similar programmable phase locked loops simultaneously generates a video clock signal and a memory clock signal. Both the video clock signal and the memory clock signal may have one of several different frequencies. The generator includes circuitry which detects when one of the selected frequencies is identical to or a submultiple of the other. The comparison circuitry which detects this condition acts to change the frequency of one of the clock signals, and supplies the other clock signal in its place. Both the video clock signal generator and the memory clock signal generator are programmable via their respective internal memories, and the internal memory of the video clock signal generator carries additional information which identifies those video frequencies which are identical to or a submultiple of the frequencies available from the memory phase locked loop.

Abstract: A new and improved clock system is described which is effective to substantially increase speed of operation of logic circuits without the need for additional power. That system includes the use of two sets of like phased clock signals, one of which is applied to the internal circuitry and the other of which controls the input and output stages of the circuit. By apportioning the capacitive load on the clock generator, the slower switching input and output circuitry is provided with faster switching clock signals exhibiting increased usable clock time while the faster switching internal circuitry is provided with less usable clock time. As a result, the available clock power is used to maximum efficiency and circuit speed is increased to the limit of the switching capabilities of the internal circuitry.