Abstract: A design structure embodied in a machine readable medium used in a design process includes an apparatus for initializing a reference cell in a toggle switched MRAM device, with a first sense amplifier configured for performing a first read operation of the reference cell by comparing current through the reference cell with the average current passing through a pair of data cells; a first latch for storing the result of the first read operation; a second latch for storing the result of a second read operation by the first sense amplifier, wherein the second read operation is performed following the first read operation and the inversion of the value of one of the pair of the data cells; a third latch for storing the result of a third read operation by the first sense amplifier, wherein the third read operation is performed following the second read operation and the inversion of the value of the other of the pair of the data cells; and a majority compare device configured to compare of the results of the first

Abstract: A method of forming a magnetic domain wall memory apparatus with write/read capability includes forming a plurality of coplanar shift register structures each comprising an elongated track formed from a ferromagnetic material having a plurality of magnetic domains therein, the shift register structures further having a plurality of discontinuities therein to facilitate domain wall location: forming a magnetic read element associated with each of the shift register structures: and forming a magnetic write element associated with each of the shift register structures, the magnetic write element further comprising a write wire having a constriction therein, the constriction located at a point corresponding to the location of one of the plurality of discontinuities in the associated shift register structure.

Abstract: A precision sense amplifier apparatus includes a current source configured to introduce an adjustable reference current through a reference leg; a current mirror configured to mirror the reference current to a data leg, the data leg selectively coupled to a programmable resistance memory element; an active clamping device coupled to the data leg, and configured to clamp a fixed voltage across the memory element, thereby establishing a fixed current sinking capability thereof; and a differential sense amplifier having a first input thereof coupled to the data leg and a second input thereof coupled to the reference leg; wherein an output of the differential sense amplifier assumes a first logic state whenever the reference current is less than the fixed current sinking capability of the memory element, and assumes a second logic state whenever the reference current exceeds the fixed current sinking capability.

Abstract: A method of determining an initial state of a reference cell in a fabricated memory array includes performing a first read operation of the reference cell by comparing current through the reference cell with the average current passing through a pair of data cells, and storing the result of the first read operation; inverting the value of one of the pair of the data cells; performing a second read operation of the reference cell, and storing the result of the second read operation; inverting the value of the other of the pair of the data cells; performing a third read operation of the reference cell, and storing the result of the third read operation. A majority compare operation of the results of the first, second and third operations is performed, wherein the result of the majority compare operation is the initial state of the reference cell.

Abstract: A magnetic domain wall memory apparatus with write/read capability includes a plurality of coplanar shift register structures each comprising an elongated track formed from a ferromagnetic material having a plurality of magnetic domains therein, the shift register structures further having a plurality of discontinuities therein to facilitate domain wall location; a magnetic read element associated with each of the shift register structures; and a magnetic write element associated with each of the shift register structures, the magnetic write element further comprising a single write wire having a longitudinal axis substantially orthogonal to a longitudinal axis of each of the coplanar shift register structures.

Abstract: A magnetic domain wall memory apparatus with write/read capability includes a plurality of coplanar shift register structures each comprising an elongated track formed from a ferromagnetic material having a plurality of magnetic domains therein, the shift register structures further having a plurality of discontinuities therein to facilitate domain wall location; a magnetic read element associated with each of the shift register structures; and a magnetic write element associated with each of the shift register structures, the magnetic write element further comprising a single write wire having a longitudinal axis substantially orthogonal to a longitudinal axis of each of the coplanar shift register structures.

Abstract: A magnetic domain wall memory apparatus with write/read capability includes a plurality of coplanar shift register structures each comprising an elongated track formed from a ferromagnetic material having a plurality of magnetic domains therein, the shift register structures further having a plurality of discontinuities therein to facilitate domain wall location; a magnetic read element associated with each of the shift register structures; and a magnetic write element associated with each of the shift register structures, the magnetic write element further comprising a write wire having a constriction therein, the constriction located at a point corresponding to the location of the plurality of discontinuities in the associated shift register structure.

Abstract: A method of determining an initial state of a reference cell in a fabricated memory array includes performing a first read operation of the reference cell by comparing current through the reference cell with the average current passing through a pair of data cells, and storing the result of the first read operation; inverting the value of one of the pair of the data cells; performing a second read operation of the reference cell, and storing the result of the second read operation; inverting the value of the other of the pair of the data cells; performing a third read operation of the reference cell, and storing the result of the third read operation. A majority compare operation of the results of the first, second and third operations is performed, wherein the result of the majority compare operation is the initial state of the reference cell.

Abstract: A calibrated magnetic random access memory (MRAM) current sense amplifier includes a first plurality of trim transistors selectively configured in parallel with a first load device, the first load device associated with a data side of the sense amplifier. A second plurality of trim transistors is selectively configured in parallel with a second load device, the second load device associated with a reference side of the sense amplifier. The first and said second plurality of trim transistors are individually activated so as to compensate for device mismatch with respect to the data and reference sides of the sense amplifier.

Abstract: A phase shift mask shape that reduces line-end shortening at the critical feature without changing layout size increases required of requisite phase shift rules. The phase feature is given an angled extension, which includes the lithographic shortening value. This allows the critical shape to be designed much closer to the reference layer then it could without the angled extension feature. Phase mask extension features beyond a given device segment are significantly reduced by lengthening the feature along an uncritical portion; moving the feature reference point to the device layer; and flattening the phase extension feature into an L-shape or T-shape along the uncritical parts of a device segment. Applying these design rules allows a draw of the gate conductor under current conditions and puts phase shapes inside without extending the gate conductor dimensions to the next feature.

Abstract: A method for determining a desired anisotropy axis angle for a magnetic random access memory (MRAM) device includes selecting a plurality of initial values for the anisotropy axis angle and determining, for each selected initial value, a minimum thickness for at least one ferromagnetic layer of the MRAM device. The minimum thickness corresponds to a predefined activation energy of an individual cell within the MRAM device. For each selected value, a minimum applied magnetic field value in a wordline direction and a bitline direction of the MRAM device is also determined so as maintain the predefined activation energy. For each selected value, an applied power per bit value is calculated, wherein the desired anisotropy axis angle is the selected anisotropy axis angle corresponding to a minimum power per bit value.

Abstract: A magneto-resistive random access memory (MRAM) array comprises global bit lines segmented using a plurality of local bit lines. A read/write controller is connected to the switches. Switches couple the global bit line to the local bit lines. The MRAM array has low leakage currents and facilitates a high signal-to-noise (S/N) ratio of read and write operations.

Abstract: A method for sensing data stored within a cross point magnetic random access memory (MRAM) device includes establishing an offset voltage of a sense amplifier, the sense amplifier selectively coupled to a selected bitline within the MRAM device, the selected bitline being in communication with an MRAM cell to be read. A read current is applied through the MRAM cell to be read, and a reference current is applied through the selected bitline. A signal voltage is sensed on the selected bitline, the signal voltage being generated in response to the read current and the reference current. The signal voltage is coupled to an input of the sense amplifier, wherein the sense amplifier provides an offset corrected output reflective of the data state of the MRAM cell.

Abstract: A method for sensing data stored within a cross point magnetic random access memory (MRAM) device includes establishing an offset voltage of a sense amplifier, the sense amplifier selectively coupled to a selected bitline within the MRAM device, the selected bitline being in communication with an MRAM cell to be read. A read current is applied through the MRAM cell to be read, and a reference current is applied through the selected bitline. A signal voltage is sensed on the selected bitline, the signal voltage being generated in response to the read current and the reference current. The signal voltage is coupled to an input of the sense amplifier, wherein the sense amplifier provides an offset corrected output reflective of the data state of the MRAM cell.

Abstract: A circuit configuration for a current switch of a bit line or a word line of a magnetoresistive random access memory (MRAM) device, comprising a directional switch and a voltage driver that, in operation, reduces the ON resistance of the directional switch. In one embodiment, each terminal of the line is provided with such a switch.

Abstract: A phase shift mask shape that reduces line-end shortening at the critical feature without changing layout size increases required of requisite phase shift rules. The phase feature is given an angled extension, which includes the lithographic shortening value. This allows the critical shape to be designed much closer to the reference layer then it could without the angled extension feature. Phase mask extension features beyond a given device segment are significantly reduced by lengthening the feature along an uncritical portion; moving the feature reference point to the device layer; and flattening the phase extension feature into an L-shape or T-shape along the uncritical parts of a device segment. Applying these design rules allows a draw of the gate conductor under current conditions and puts phase shapes inside without extending the gate conductor dimensions to the next feature.

Abstract: The present invention relates to a method and apparatus for reducing data errors in a magneto-resistive random access memory (MRAM). According to the disclosed method, data bits and associated error correction code (ECC) check bits are stored into a storage area. Thereafter, the data bits and ECC check bits are read out and any errors are detected and corrected. A data refresh is then initiated based on a count and data bits and associated ECC check bits stored in the storage area are then refreshed by accessing the stored data bits and the associated ECC check bits, and ultimately by checking, correcting and restoring the data bits and the ECC check bits to the storage area.

Abstract: An isolation and gate planarization method for an integrated circuit chip and chips designed by the method. The method comprises generating a dummy gate conductor (GC) shape and biasing it to the underlying well. The method may further comprise generating an active area (AA) dummy shape underlying the GC dummy shape. Biasing may be to the same voltage as the underlying well, or may be to a different voltage to create a decoupling capacitor. The biasing may be accomplished by implanting a well contact on an active area shape, the contact being N+ over an N-well or P+ over a P-well.

Abstract: A method for obtaining equalization voltages that are a fraction of bit line high other than ½ in a DRAM semiconductor circuit, and an associated circuit, in arrangements that include a plurality of block cell arrays with a plurality of complementary pairs of bit lines connected to each block array with control lines to selectively activate a desired array block. Each block uses shared sense amplifiers connected to the pairs of bit lines and there is an equalization circuit connected between each of the bit line pairs of each of the array blocks, between each of the array blocks and the shared sense amplifiers. A charge flow circuit is also connected between each of the bit line pairs of each of the array blocks, between each of the array blocks and the shared sense amplifiers. A charge flow circuit control line is connected to the charge flow circuits for connecting the charge flow circuit to an electrical ground, thereby to act as a discharge circuit or to the bit line high voltage.

Abstract: A semiconductor device having a compact folded bitline architecture. Bitlines for a memory cell array arranged into bitline pairs constituting, when in use, a selected bitline and its complement. The selected bitline and its complement are adjacent in upper and lower levels, and exchange levels at selected breakpoints in the lower level bitline. The breakpoints are determined so as to establish a diagonally-oriented pattern of “twist regions” across the array. Adjacent bitline pairs exchange levels in alternating twist regions. The upper bitlines are positioned at a predetermined angle, relative to the lower bitlines, in selected intervals between the twist regions. The predetermined angle introduces an offset between the upper bitlines and their associated complement lower bitlines as the upper bitlines enter twist regions to exchange levels.